Exploring Ethernet Switching Architectures for Area-Efficient Low-End Switches

Abstract

The aim of this thesis project has been to develop an architecture for L2 ethernet switches that would be optimized for silicon area, targeting smaller low-end
switches. A selection was made of three different switching architectures, which
were compared and analyzed to explore the benefits and drawbacks of different
approaches. From these, one architecture called Shared Memory Linked-List was
selected that served as a base to develop a new area-efficient architecture. This architecture was implemented in the form of two different port configurations using
MyHDL to generate Verilog code, which was used for behavioral simulation. The
RTL code was synthesized into both an FPGA and ASIC implementation which
was compared to a contemporary alternative in the form of an equivalent ethernet
switch generated by the FlexSwitch tool suite developed by Packet Architects AB.
The four-port configuration of the thesis implementation showed significant area
reductions in the buffer management subsystems for both the FPGA and ASIC
versions, while the ten-port configuration showed a similar reduction in the ASIC
version, while the FPGA implementation decreased the usage of certain hardware
components while others increased. An analysis of the architecture, its benefits,
and drawbacks was performed and potential future improvements were suggested.

Popular Abstract

Ethernet switches are electronic devices that serve a very important role in the
modern internet. These devices could be seen as some sort of traffic controller
that takes data that is being sent over the internet and ensures that it continues
to travel toward its correct destination. Ethernet switches can be found in large
data centers, office buildings, homes, and even inside other machines. When you
are sending data over the internet in any form, be it sending an e-mail, or uploading
a photo to a website, that information will travel from your computer through a
long series of switches that forward it before it finally reaches its destination.
Another thing that is interesting about ethernet switches is the fact that they
come in all shapes and sizes. The switches that you might have seen in a data
center are very large and contain hundreds or thousands of ports connected to
ethernet cables, while the ones you see in an office or home are much smaller and
could contain less than ten ports. The fact that these devices vary so greatly
in size, means that the underlying design and architecture of how the switch is
constructed becomes quite important. The way in which you build a data center
switch that is the size of a large closet, might not be an ideal way to build one that
is the size of a DVD case. This is the case since even though both of these machines
are performing the same tasks, the way in which they do it might be completely
different. A very large switch must be built to be as fast as possible, while a smaller
one might have to consume less power or be as small as possible. There exists
plenty of research regarding how one should build very large switches effectively,
but there seems to be an apparent knowledge gap regarding architectures that are
well suited for smaller switches. This is the gap that this thesis work attempted
to start filling.
The thesis goal was to produce an efficient architecture for constructing smaller
"low-end" ethernet switches. This architecture was constructed to minimize the
total area of the switch, since for a low-end switch, making it smaller can be
deemed more important than making it faster. This was done by selecting and
comparing different existing architectures so that their respective benefits and
drawbacks could be studied. These architectures were in some ways combined
with each other as well as with some ideas of our own in order to produce the final
architecture. Finally, the architecture was actually built. In order to measure its
"area-efficiency", its size was compared against a contemporary alternative in the
form of ethernet switches produced by the company Packet Architects AB. The results showed that the thesis architecture enabled significant area reductions for
certain parts of the switch, but also that this architecture does not seem to be well
suited for larger switches.

• author: Swedberg, Jon and Ghosh, Felix
• supervisor: Liang Liu
• organization: Department of Electrical and Information Technology
• course: EITM01 20231
• year: 2023
• type: H2 - Master's Degree (Two Years)
• subject: Technology and Engineering
• keywords: Ethernet Switch, Architecture, Silicon Area, Area Optimization, ASIC, FPGA
• report number: LU/LTH-EIT 2023-920
• language: English
• id: 9133542
• date added to LUP: 2023-08-07 13:39:54
• date last changed: 2023-08-07 13:39:54