High-Speed Serial Link for Low-Power Memories

Abstract (Swedish)

A bidirectional serial link on-chip implementation is going to be assessed so as to
set the option of using it as a replacement of the actual parallel interconnection
used to transfer data between different memory banks in an embedded low-power
memory unit. Asynchronous communication is the protocol selected and current
mode pulse signaling is the technique used to transfer data. A 32-bit data packet is
transmitted with a throughput of 10.66 Gbps. The interconnect was designed using
28nm CMOS BULK technology from TSMC and was simulated with Cadence
Analog Spectre; it occupies 902.21 μm 2 and consumes 4.93 pJ/bit. The research
was done in collaboration with the company Xenergic.

Popular Abstract

Electronic devices play an important role in different aspects of our daily lives. We
are surrounded by gadgets that possess a lot of features and in order to make this
possible, the integration of different systems within a single chip is necessary. The
development of new technologies and innovation in circuit design are required in
order to be able to increase the functionalities of a chip, optimize area and minimize
energy consumption. Among different types of circuits that exist, memories are an
important element and one of the biggest building blocks within a chip, so when
designing memories, area is always a concern and a parameter to optimize.
The information that is going to be used and processed by other circuits, is
usually stored and read from a memory. This information (data) will be transferred
across different functional units and in order to do so, wires routed in parallel
are commonly used. This is a critical aspect that needs to be improved since
it represents a high area cost. Moreover, different phenomena arise when having
metals routed in parallel, which in turn represent a detriment in the overall system
performance.
That is why this thesis aims to assess the cost of replacing the parallel inter-
connection with a serial link in order to optimize area. One of the concerns of
doing so, is to be able to transfer the same amount of data per unit time as with
a parallel link. The reason of it, is that in order to make this possible, the system
needs to operate at higher clock frequencies.
On-chip communication can be synchronous, meaning that transmission and
reception of data are both coordinated with one another by using the same clock
signal, or it can be asynchronous, meaning that the transmitter and the receiver
are timed independently from each other. In this thesis, the asynchronous com-
munication protocol is implemented, since it is simpler and less expensive.
Data representation and proper modeling of the transmission channels are nec-
essary in order to design the system’s circuits. Proper architectures were selected
in order to accomplish data transfer at the required speed.
The initial assessment results show that the proposed system is a viable solu-
tion for intermemory communication that can be implemented as a way of memory
design optimization.

• author: Melendez Rasgado, Anely Catalina
• supervisor: Babak Mohammadi
• organization: Department of Electrical and Information Technology
• course: EITM02 20181
• year: 2018
• type: H2 - Master's Degree (Two Years)
• subject: Technology and Engineering
• keywords: Serial, communication, memories, high speed
• report number: LU/LTH-EIT 2018-658
• language: English
• id: 8951707
• date added to LUP: 2018-08-24 08:59:39
• date last changed: 2018-08-24 08:59:39