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- 2019
-
Mark
Methodology For Improving performance & Reliability In Low Voltage on-chip Memories
(
- Master (Two yrs)
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Mark
A Technology Agnostic Approach for Standard-cell Layout Design Automation
(
- Master (Two yrs)
-
Mark
Design of High Speed in Memory Serializer/Deserializer with Integrated Sense Amplifier
(
- Master (Two yrs)
-
Mark
Statistical Approach for the Design of Refresh-Free eDRAM with Retention Timing Constraint
(
- Master (Two yrs)
- 2018
-
Mark
Access-rate guaranteed memory controller
(
- Master (Two yrs)
-
Mark
High-Speed Serial Link for Low-Power Memories
(
- Master (Two yrs)
- 2016
-
Mark
Design of a Memory Compiler
(
- Master (Two yrs)