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Design of a Memory Compiler

Gustavsson, John LU and Andersson, Axel LU (2016) EITM01 20161
Department of Electrical and Information Technology
Abstract
Memory compilers are typically intellectual property of memory vendors. The
purpose of compilers is to automatically generate various kinds of memories depending on the customer order. These compilers support the generation of various memory capacities as well as static random-access memory (SRAM) types, e.g., single- and dual-port memories. Discrepancy between the customers requirements and vendors portfolio are typically left to be solved by the customer. This results in a remarkable extra engineering effort, if an optimized SRAM solution is desired. In order to reduce this engineering overhead and quality enhancement a more flexible memory compiler was developed.

The purpose of this project is to develop a memory compiler for a new... (More)
Memory compilers are typically intellectual property of memory vendors. The
purpose of compilers is to automatically generate various kinds of memories depending on the customer order. These compilers support the generation of various memory capacities as well as static random-access memory (SRAM) types, e.g., single- and dual-port memories. Discrepancy between the customers requirements and vendors portfolio are typically left to be solved by the customer. This results in a remarkable extra engineering effort, if an optimized SRAM solution is desired. In order to reduce this engineering overhead and quality enhancement a more flexible memory compiler was developed.

The purpose of this project is to develop a memory compiler for a new SRAM architecture designed at the Department of Electrical and Information Technology at Lund University. The compiler provides the necessary functionality to generate memories in various sizes and with different types of bitcells. The compiler will be used by a co-project to generate a high-speed SRAM with dual-port support, which is going to be fabricated. The work will be available for further thesis’s to improve and add functionality. The compiler was developed in Cadence Virtuoso using the scripting language SKILL as the primary tool. The flow was evaluated for two different technologies, 65 and 28 nm. Performance simulations were performed to determine the constraints and bottlenecks. Parasitic modelling of the memory was performed in Verilog-A for simulation purposes.

Using a script based design approach will result in a configurable, reliable and fast design flow. It was concluded that a strong framework has to be set up for the layout designer to follow due to the script limits. Using a parasitic model of a bitcell block was found to be excellent for simulation purposes. Improving the simulation time of a 4 kb memory by a factor of 11 and keeping the most significant parasitic information. (Less)
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author
Gustavsson, John LU and Andersson, Axel LU
supervisor
organization
course
EITM01 20161
year
type
H2 - Master's Degree (Two Years)
subject
keywords
SRAM, Memory, Compiler, Memory Compiler, 6T, 7T, 8T, Dual-port, High Speed, bitcell
report number
LU/LHT-EIT 2016-553
language
English
id
8896304
date added to LUP
2016-12-21 14:58:33
date last changed
2018-05-14 11:11:35
@misc{8896304,
  abstract     = {Memory compilers are typically intellectual property of memory vendors. The
purpose of compilers is to automatically generate various kinds of memories depending on the customer order. These compilers support the generation of various memory capacities as well as static random-access memory (SRAM) types, e.g., single- and dual-port memories. Discrepancy between the customers requirements and vendors portfolio are typically left to be solved by the customer. This results in a remarkable extra engineering effort, if an optimized SRAM solution is desired. In order to reduce this engineering overhead and quality enhancement a more flexible memory compiler was developed.
 
The purpose of this project is to develop a memory compiler for a new SRAM architecture designed at the Department of Electrical and Information Technology at Lund University. The compiler provides the necessary functionality to generate memories in various sizes and with different types of bitcells. The compiler will be used by a co-project to generate a high-speed SRAM with dual-port support, which is going to be fabricated. The work will be available for further thesis’s to improve and add functionality. The compiler was developed in Cadence Virtuoso using the scripting language SKILL as the primary tool. The flow was evaluated for two different technologies, 65 and 28 nm. Performance simulations were performed to determine the constraints and bottlenecks. Parasitic modelling of the memory was performed in Verilog-A for simulation purposes.

Using a script based design approach will result in a configurable, reliable and fast design flow. It was concluded that a strong framework has to be set up for the layout designer to follow due to the script limits. Using a parasitic model of a bitcell block was found to be excellent for simulation purposes. Improving the simulation time of a 4 kb memory by a factor of 11 and keeping the most significant parasitic information.},
  author       = {Gustavsson, John and Andersson, Axel},
  keyword      = {SRAM,Memory,Compiler,Memory Compiler,6T,7T,8T,Dual-port,High Speed,bitcell},
  language     = {eng},
  note         = {Student Paper},
  title        = {Design of a Memory Compiler},
  year         = {2016},
}