A Technology Agnostic Approach for Standard-cell Layout Design Automation
(2019) EITM01 20191Department of Electrical and Information Technology
- Abstract
- The logic scaling following Moores law has reached a level where System on Chips
(SoCs) commonly contains millions of standard cells. The sheer amount implies
that even small optimizations on a standard cell can have a significant effect on
the SoC performance. To ensure the performance of standard cells, many of these
are hand-drawn. This is a tedious task that needs to be done every time a new
process technology emerges. Something which requires both many man-hours and
that holds a risk of designing sub-optimal solutions or introducing human error
into the design.
Presented in this thesis is a method for automatizing the complete design
process of standard cell layouts, requiring only a netlist and a few fundamental
design... (More) - The logic scaling following Moores law has reached a level where System on Chips
(SoCs) commonly contains millions of standard cells. The sheer amount implies
that even small optimizations on a standard cell can have a significant effect on
the SoC performance. To ensure the performance of standard cells, many of these
are hand-drawn. This is a tedious task that needs to be done every time a new
process technology emerges. Something which requires both many man-hours and
that holds a risk of designing sub-optimal solutions or introducing human error
into the design.
Presented in this thesis is a method for automatizing the complete design
process of standard cell layouts, requiring only a netlist and a few fundamental
design rules for the given technology. The overall procedure was divided into three
parts: placement, routing, and evaluation. The tool is entirely built in Python and
for functionality verification commercial EDA tools from CadenceTM were used.
The generated standard cells have shown to match the area requirements of typical
industry-level standard cells and in some critical complex cells even outperform
them. (Less) - Popular Abstract
- Moore’s Law states that the number of components on a chip will double every 18
months and today, a single Integrated Circuit (IC) can contain over 20,000,000,000
transistors [1]. This astronomical number makes it clear that a fully manual IC
design process isn’t realistic. Instead, an increasing level of automation is being
implemented in the field of IC design to minimize the workload and to keep time
to market as low as possible.
Standard cells are used to implement fundamental logic, such as AND, OR,
XOR and INV into compact hardware blocks that are used in typical digital ICs.
Hence, standard cells are often considered as the smallest building blocks and its
critical to optimize these building blocks for Power, Performance... (More) - Moore’s Law states that the number of components on a chip will double every 18
months and today, a single Integrated Circuit (IC) can contain over 20,000,000,000
transistors [1]. This astronomical number makes it clear that a fully manual IC
design process isn’t realistic. Instead, an increasing level of automation is being
implemented in the field of IC design to minimize the workload and to keep time
to market as low as possible.
Standard cells are used to implement fundamental logic, such as AND, OR,
XOR and INV into compact hardware blocks that are used in typical digital ICs.
Hence, standard cells are often considered as the smallest building blocks and its
critical to optimize these building blocks for Power, Performance and Area (PPA).
Designing the layout of standard cells can be a tedious task that is often drawn
manually. Currently, most standard cells (as well as most other analog layout
designs) are manually redesigned for every new process technology that emerges
because of the new sizings and design rules that follow with them.
In this thesis, a generic approach for automating the design of standard cells
is presented. The approach is designed in a way such that a minimal amount of
technology-specific information is needed while still producing efficient cells. This
would allow digital IC designers who receive a new technology to quickly generate
a library to get going with their designs, even before achieving detail knowledge
about their design rules. (Less)
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/student-papers/record/9001291
- author
- Johansson, Tom LU
- supervisor
- organization
- course
- EITM01 20191
- year
- 2019
- type
- H2 - Master's Degree (Two Years)
- subject
- keywords
- IC, automation, standard cell, standard cell design, ASIC, chip, graph theory, SAT, full adder, adder, MUX, layout, schematic, mst, minimum spanning tree, kruskal, pnr, placement, routing
- report number
- LU/LTH-EIT 2019-738
- language
- English
- id
- 9001291
- date added to LUP
- 2020-01-17 11:22:35
- date last changed
- 2020-01-17 11:22:35
@misc{9001291, abstract = {{The logic scaling following Moores law has reached a level where System on Chips (SoCs) commonly contains millions of standard cells. The sheer amount implies that even small optimizations on a standard cell can have a significant effect on the SoC performance. To ensure the performance of standard cells, many of these are hand-drawn. This is a tedious task that needs to be done every time a new process technology emerges. Something which requires both many man-hours and that holds a risk of designing sub-optimal solutions or introducing human error into the design. Presented in this thesis is a method for automatizing the complete design process of standard cell layouts, requiring only a netlist and a few fundamental design rules for the given technology. The overall procedure was divided into three parts: placement, routing, and evaluation. The tool is entirely built in Python and for functionality verification commercial EDA tools from CadenceTM were used. The generated standard cells have shown to match the area requirements of typical industry-level standard cells and in some critical complex cells even outperform them.}}, author = {{Johansson, Tom}}, language = {{eng}}, note = {{Student Paper}}, title = {{A Technology Agnostic Approach for Standard-cell Layout Design Automation}}, year = {{2019}}, }