Statistical Approach for the Design of Refresh-Free eDRAM with Retention Timing Constraint
(2019) EITM02 20181Department of Electrical and Information Technology
- Abstract
- In digital integrated circuits, memories are often a limiter for main performance, power and area. Over the past decade, integrated memories have gained dominance in terms of area and power cost. In applications like machine learning or image processing the area share can be above 80% consuming more than 50% of the total power budget. On-chip memories in CMOS technologies can be categorized as static (SRAM) and dynamic (embedded DRAM). SRAM has been the main choice due to its high-access rates and static data retention feature. eDRAM offers higher area gain over SRAM counterpart. However, dynamic memories require periodic, power-hungry refresh operations. This operations increase the design complexity and have a high energy cost.... (More)
- In digital integrated circuits, memories are often a limiter for main performance, power and area. Over the past decade, integrated memories have gained dominance in terms of area and power cost. In applications like machine learning or image processing the area share can be above 80% consuming more than 50% of the total power budget. On-chip memories in CMOS technologies can be categorized as static (SRAM) and dynamic (embedded DRAM). SRAM has been the main choice due to its high-access rates and static data retention feature. eDRAM offers higher area gain over SRAM counterpart. However, dynamic memories require periodic, power-hungry refresh operations. This operations increase the design complexity and have a high energy cost. Furthermore, they lower the access rates due to memory restriction during refresh periods, which makes it less desirable in SoC context.
A wide range of computation intensive applications in today's digital systems need to buffer intermediate data for a short fraction of time. Multiple Input Multiple Output (MIMO) communication and convolutional image processing are two cases that use memories for storing data during short time periods. These are appropriate applications for the use of eDRAM without refresh operations.
The goal of this study is to evaluate and develop an eDRAM memory compiler. This compiler evaluates the design of an eDRAM cell and considers the effect of manufacturing process deviations. These variations are based on statistics, and for their analysis, a new statistical approach 100 times faster than the generally used analysis method is developed. The output of the compiler is a macro layout according to the eDRAM cell and results from the statistical design evaluation. The final result is a tool that allows the automatic generation of eDRAM as a function of user requirements. (Less) - Popular Abstract
- Memories have an important role in electronic devices with a strong impact in the performance, power and area of digital integrated circuits. The constant increase in data flow intensifies the effect of memories in the design. For example, image processing applications require the storing of one image at a time for their processing. Once an image has been processed, a new image is overwritten in the memory. The data is stored momentary according to the processing period. The temporary storage of these applications is appropriate for the use of memories based in non-static data retention.
Embedded dynamic memories (eDRAM) are a good alternative for the memory implementation in these applications. They use less number of transistors, which... (More) - Memories have an important role in electronic devices with a strong impact in the performance, power and area of digital integrated circuits. The constant increase in data flow intensifies the effect of memories in the design. For example, image processing applications require the storing of one image at a time for their processing. Once an image has been processed, a new image is overwritten in the memory. The data is stored momentary according to the processing period. The temporary storage of these applications is appropriate for the use of memories based in non-static data retention.
Embedded dynamic memories (eDRAM) are a good alternative for the memory implementation in these applications. They use less number of transistors, which represents an area save compare to other possible solutions. The dynamic character of eDRAM require refresh operations, increasing power and restricting the memory access during these operations. However, in applications like image processing, it is possible to design the memory according to the processing period, been able to remove the power-hungry refresh operations. This thesis aims to implement a memory compiler for the automatic generation of Refresh-Free eDRAM according to the application requirements.
Other requirement for the memory generation is the effect of process variations in the design. They are determined by the manufacturing process and affect to the reliability of digital circuits. The trend of reduction in transistor dimensions provides reduction in area cost of circuit implementations. However, it entails more manufacturing difficulties, increasing the effect of process variations. In order to ensure the reliability of the design, the effect of process variations is part of the compiler for the automatic generation of Refresh-Free eDRAM. (Less)
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/student-papers/record/8974784
- author
- Prieto, Arturo LU
- supervisor
- organization
- course
- EITM02 20181
- year
- 2019
- type
- H2 - Master's Degree (Two Years)
- subject
- keywords
- Memory, eDRAM, DRAM, SRAM, IC, Refresh, Statistics, Importance Sampling, Monte Carlo
- report number
- LU/LTH-EIT 2019-690
- language
- English
- id
- 8974784
- date added to LUP
- 2019-04-26 10:52:20
- date last changed
- 2019-04-26 10:52:20
@misc{8974784,
abstract = {{In digital integrated circuits, memories are often a limiter for main performance, power and area. Over the past decade, integrated memories have gained dominance in terms of area and power cost. In applications like machine learning or image processing the area share can be above 80% consuming more than 50% of the total power budget. On-chip memories in CMOS technologies can be categorized as static (SRAM) and dynamic (embedded DRAM). SRAM has been the main choice due to its high-access rates and static data retention feature. eDRAM offers higher area gain over SRAM counterpart. However, dynamic memories require periodic, power-hungry refresh operations. This operations increase the design complexity and have a high energy cost. Furthermore, they lower the access rates due to memory restriction during refresh periods, which makes it less desirable in SoC context.
A wide range of computation intensive applications in today's digital systems need to buffer intermediate data for a short fraction of time. Multiple Input Multiple Output (MIMO) communication and convolutional image processing are two cases that use memories for storing data during short time periods. These are appropriate applications for the use of eDRAM without refresh operations.
The goal of this study is to evaluate and develop an eDRAM memory compiler. This compiler evaluates the design of an eDRAM cell and considers the effect of manufacturing process deviations. These variations are based on statistics, and for their analysis, a new statistical approach 100 times faster than the generally used analysis method is developed. The output of the compiler is a macro layout according to the eDRAM cell and results from the statistical design evaluation. The final result is a tool that allows the automatic generation of eDRAM as a function of user requirements.}},
author = {{Prieto, Arturo}},
language = {{eng}},
note = {{Student Paper}},
title = {{Statistical Approach for the Design of Refresh-Free eDRAM with Retention Timing Constraint}},
year = {{2019}},
}