Methodology For Improving performance & Reliability In Low Voltage on-chip Memories

Abstract

Recent surveys show that on average about 70% of the area budget of the system on chip
(SoC) is occupied by Static Random Access Memory (SRAM)s, with a capacity
ranging from a few kilo-bits to tens of megabits. SRAM (static RAM or SRAM)
is a type of electronic memory that uses bistable latching circuitry (flip-flop) to
store each bit. SRAM is volatile in the conventional sense that data is eventually
lost when the memory is not powered. The term static differentiates SRAM from
DRAM (dynamic random-access memory) which must be periodically refreshed.
SRAM is faster and more expensive than DRAM; it is typically used for CPU cache
while DRAM is used for a computer's main One critical issue in modern SoCs when
using such huge amount of on-chip memories is area efficiency. The other vital
factor is power consumption. One desired approach in designing memories is to
reduce power consumption by lowering the voltage but pay as little as possible in
terms of silicon area overhead. Low-power memory design is a challenging eld
that designers need to push the energy and area efficiency to extreme limits.
In this thesis, the main goal will be to look into different approaches or techniques
on how to maintain the low power SRAM memories functionality in terms of R/W
reliability in low voltage operations.
One useful technique is to be able to temporarily boost the voltage locally for
desired nodes in the circuit without having to raise the operational SRAM supply
voltage. So, a specially designed in-memory charge pump would be beneficial with
the condition that the intrinsic large parasitic capacitances already existing on the
memory is exploited for this purpose; hence keeping area overhead to a minimum.
One other limitation in low voltage SRAMs is the sense amplifier. These circuits
elements are generally working well with the nominal SRAM voltages verified for a
certain technology node. However, special considerations require when the intention is to reduce the supply voltage. This requires to take a fresh look into sense
amplifier implementations and propose a more suitable approach regarding theses
elements of SRAM memories in low voltages. This might demand to introduce new circuit elements to the memory design. For example in the case under some
certain conditions using single-ended sense amplifiers shown to be beneficial, there
might be a need to design circuits to provide the required reference voltages for
their operations.
Consequently, the following are some key steps for the thesis and will be used as
milestones or goals:
• Investigating the possibility of using in-memory charge pump circuitry to
provide local voltage boosting in desired memory nodes with the intention
of maintaining acceptable R/W reliability in low power memories. Cares
must be taken to avoid introducing unnecessarily extra area overhead to the
memory layout.
• Investigating and proposing sense amplifier circuitry which is more suitable
for low voltage SRAM memories.
• Implementing a voltage reference generator to be used for sense amplifier diversity schemes to improve detection reliability; e.g. using single-ended sense
amplifier circuits in combination with a differential one to enhance memory
cell read reliability.

Popular Abstract

Static Random Access Memory (Static RAM or SRAM) is a type of RAM that
holds data in static form, that stays available, as long as the memory is supplied
by power. SRAM is best suited for operations like the CPU's fast cache memory
and storing registers, hard drives as disc cache, printers, modems routers, and
digital cameras. SRAM stores a bit of data on four transistors that form two
cross-coupled inverters named Cell. Cells are positioned in matrix shape comprise
columns and rows to make a bigger memory. Place of the cell determines by
columns and rows order which makes up the address of memory cell. Access to
each cell is facilitated by decoding the address by the decoder and multiplexer and
selecting the associated column and rows provides access to determined bit-cell for
read and write operations. Read means putting data on a specic cell and write
means detecting the content of a certain cell.
The requirements to keep more data buering capacities lead to Increasing onchip memory density trend is driven eorts to scale the size of bit-cell [1] thanks
to technology improvements. On the other hand, scaling faces the limitation of
scaling threshold voltage Vt [3], [4]. Size scaling contributes to a higher density
of cells and lowers voltage grant lower power consumption that is in the center of
attention in IoT applications [2]. Reducing the supply voltage aects the read and
writes operations [4]. Some techniques developed to compensate for the read and
write operation parameters in lower voltages. One of these techniques is adjusting
the voltage of critical nodes to improve the performance of SRAM [1]. There are
peripheral circuits to facilitate the read and write operations on bit-cell. During
the read operation, the content of the bit-cell is detected by a sense amplier. A
sense amplier is a kind of circuit that amplies a small input dierential voltage to
a large rail to rail voltage dierence at the output. A column of cells is connected
to the sense amplier and during the read operation sense amplier demonstrates
the content of certain cells that are selected by addressing procedure. Provided
failure of the sense amplier a column of bit cells failed to work. Enhancing sense
amplifer function saves a major part of memory cells. This thesis concentrates
on peripheral circuits to improve SRAM read and write operations in low voltage
conditions.

• author: Movahedimeimandi, Hamed
• supervisor: Henrik Sjöland; Babak Mohammadi
• organization: Department of Electrical and Information Technology
• course: EITM02 20191
• year: 2019
• type: H2 - Master's Degree (Two Years)
• subject: Technology and Engineering
• keywords: Low power memories, Assist technique, Voltage Boosting, Charge pump, Sense amplifier, Voting method.
• report number: LU/LTH-EIT 2019-727
• language: English
• id: 8995375
• date added to LUP: 2019-09-27 14:48:35
• date last changed: 2019-09-27 14:48:35