An Optimized Hardware Implementation of Grain-128AEAD
(2019) EITM01 20191Department of Electrical and Information Technology
- Abstract
- With the Internet of Things era being here, more devices than ever are connected to the Internet, making the need for higher security greater. One important aspect of security to consider is encryption, which protects data from being read by unauthorized parties. Integrating cryptographic algorithms can be done in many ways and is usually dependent on restrictions of the area, speed, and power when it comes to hardware. One way of integrating security into hardware is with the use of stream ciphers, which can be very efficient in terms of power, area, and speed.
In this thesis, we present different implementations of Grain-128AEAD, which is a new stream cipher that can encrypt and decrypt data as well as provide authentication for the... (More) - With the Internet of Things era being here, more devices than ever are connected to the Internet, making the need for higher security greater. One important aspect of security to consider is encryption, which protects data from being read by unauthorized parties. Integrating cryptographic algorithms can be done in many ways and is usually dependent on restrictions of the area, speed, and power when it comes to hardware. One way of integrating security into hardware is with the use of stream ciphers, which can be very efficient in terms of power, area, and speed.
In this thesis, we present different implementations of Grain-128AEAD, which is a new stream cipher that can encrypt and decrypt data as well as provide authentication for the data. The implementations are optimized both on a hardware level, synthesis level and transistor level for different restrictions of area, power, and speed. The optimizations on hardware level include Galois transformation, isolation, pipelining and a transformation of the output function. For the synthesis level optimizations, we developed three scripts: one for reducing area/power with low power transistors (HVT) and two for increasing speed with high-speed transistors (LVT). On a transistor level, we optimized the Boolean expressions present in the feedback and output functions of the cipher.
In addition to that, we also present a new 64 times parallelization of Grain-128AEAD by allowing connections between the feedback and output functions of the cipher.
The combined effect of all the optimizations enabled the cipher to run at a throughput of 1.25-33.6 Gb/s compared to the 1-19 Gb/s throughput for the non-optimized versions. The area also improved by approximately 2-7\% with the low area/power script, while the transistor level optimizations further reduced it by approximately 1-12\% for the different parallelized versions. In addition to that, the power improved by up to 37\% and 92\% at 10 MHz and 100 KHz respectively. (Less)
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/student-papers/record/8991149
- author
- Sönnerup, Mattias LU and Khattar, Ripudaman
- supervisor
-
- Martin Hell LU
- Jonathan Sönnerup LU
- organization
- course
- EITM01 20191
- year
- 2019
- type
- H2 - Master's Degree (Two Years)
- subject
- report number
- LU/LTH-EIT 2019-717
- language
- English
- id
- 8991149
- date added to LUP
- 2019-08-19 11:17:21
- date last changed
- 2019-08-19 11:17:21
@misc{8991149,
abstract = {{With the Internet of Things era being here, more devices than ever are connected to the Internet, making the need for higher security greater. One important aspect of security to consider is encryption, which protects data from being read by unauthorized parties. Integrating cryptographic algorithms can be done in many ways and is usually dependent on restrictions of the area, speed, and power when it comes to hardware. One way of integrating security into hardware is with the use of stream ciphers, which can be very efficient in terms of power, area, and speed.
In this thesis, we present different implementations of Grain-128AEAD, which is a new stream cipher that can encrypt and decrypt data as well as provide authentication for the data. The implementations are optimized both on a hardware level, synthesis level and transistor level for different restrictions of area, power, and speed. The optimizations on hardware level include Galois transformation, isolation, pipelining and a transformation of the output function. For the synthesis level optimizations, we developed three scripts: one for reducing area/power with low power transistors (HVT) and two for increasing speed with high-speed transistors (LVT). On a transistor level, we optimized the Boolean expressions present in the feedback and output functions of the cipher.
In addition to that, we also present a new 64 times parallelization of Grain-128AEAD by allowing connections between the feedback and output functions of the cipher.
The combined effect of all the optimizations enabled the cipher to run at a throughput of 1.25-33.6 Gb/s compared to the 1-19 Gb/s throughput for the non-optimized versions. The area also improved by approximately 2-7\% with the low area/power script, while the transistor level optimizations further reduced it by approximately 1-12\% for the different parallelized versions. In addition to that, the power improved by up to 37\% and 92\% at 10 MHz and 100 KHz respectively.}},
author = {{Sönnerup, Mattias and Khattar, Ripudaman}},
language = {{eng}},
note = {{Student Paper}},
title = {{An Optimized Hardware Implementation of Grain-128AEAD}},
year = {{2019}},
}