Test and Repair of Reconfigurable On-chip Instrument Access Networks
(2019) EITM02 20191Department of Electrical and Information Technology
- Abstract
- As transistors in integrated circuits (ICs) are becoming smaller, faster and more, it has become harder to avoid malfunctioning. Embedded instruments are increasingly used to test, tune, and configure the transistors in ICs. IEEE Std.1149.1-2013 and IEEE Std.1687 standardize the access to these embedded instruments. IEEE Std.1687 enables reconfigurable scan networks which allow only desirable instruments to be included in the active scan-path. Reconfigurable scan networks can become faulty, which may lead to the situation there will be no possibility left to test, trim and configure the IC. In this thesis, we focused on the test and repair of the faulty scan registers. We have introduced two solutions, based on the hardware and software,... (More)
- As transistors in integrated circuits (ICs) are becoming smaller, faster and more, it has become harder to avoid malfunctioning. Embedded instruments are increasingly used to test, tune, and configure the transistors in ICs. IEEE Std.1149.1-2013 and IEEE Std.1687 standardize the access to these embedded instruments. IEEE Std.1687 enables reconfigurable scan networks which allow only desirable instruments to be included in the active scan-path. Reconfigurable scan networks can become faulty, which may lead to the situation there will be no possibility left to test, trim and configure the IC. In this thesis, we focused on the test and repair of the faulty scan registers. We have introduced two solutions, based on the hardware and software, to test the reconfigurable scan network, to identify faulty scan registers, and repair the network by excluding the faulty scan register from the network. We did two experiments to measure the overhead in terms of area and data. Here, the data overhead is the data needed to be sent to IC for testing and repairing the reconfigurable network. From these experiments, we found both the solutions have unique advantages. The software solution does not use hardware area, while the hardware solution results in low data overhead. (Less)
- Popular Abstract
- The integrated circuits (ICs) consist of transistors, which are the basic components of an electronic circuit. Nowadays, transistors in integrated circuits become smaller and smaller, which increases the impact of errors in the design and manufacturing process.
Facing this problem, it becomes an important task for designers to monitor the errors of various instruments of electronic devices. In order to achieve this goal, a solution has been developed that integrate IC monitoring, testing and debugging components in the manufacturing process. These basic components are called on-chip instruments.
Since the instrument is built into the chip, additional infrastructure is needed to make the environment accessible. This is called the... (More) - The integrated circuits (ICs) consist of transistors, which are the basic components of an electronic circuit. Nowadays, transistors in integrated circuits become smaller and smaller, which increases the impact of errors in the design and manufacturing process.
Facing this problem, it becomes an important task for designers to monitor the errors of various instruments of electronic devices. In order to achieve this goal, a solution has been developed that integrate IC monitoring, testing and debugging components in the manufacturing process. These basic components are called on-chip instruments.
Since the instrument is built into the chip, additional infrastructure is needed to make the environment accessible. This is called the reconfigurable scan network. This kind of network connects with instruments through registers, which are called scan registers. Scan registers can become faulty, which may lead to the situation there will be no possibility left to test, trim and configure the IC.
In this thesis, we have introduced two solutions, based on the hardware and software, to test the reconfigurable scan network, to identify faulty scan registers, and repair the network by excluding the faulty scan register from the network. Both solutions have unique advantages. The software solution does not use hardware area, while the hardware solution results in terms of low data exchanged between the chip and environment(known as data overhead). (Less)
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/student-papers/record/8996593
- author
- Xiang, Zehang LU
- supervisor
- organization
- course
- EITM02 20191
- year
- 2019
- type
- H2 - Master's Degree (Two Years)
- subject
- keywords
- reconfigurable network, Test and repair of reconfigurable scan network, scan register
- report number
- LU/LTH-EIT 2019-736
- language
- English
- id
- 8996593
- date added to LUP
- 2019-11-05 15:19:15
- date last changed
- 2019-11-05 15:19:15
@misc{8996593,
abstract = {{As transistors in integrated circuits (ICs) are becoming smaller, faster and more, it has become harder to avoid malfunctioning. Embedded instruments are increasingly used to test, tune, and configure the transistors in ICs. IEEE Std.1149.1-2013 and IEEE Std.1687 standardize the access to these embedded instruments. IEEE Std.1687 enables reconfigurable scan networks which allow only desirable instruments to be included in the active scan-path. Reconfigurable scan networks can become faulty, which may lead to the situation there will be no possibility left to test, trim and configure the IC. In this thesis, we focused on the test and repair of the faulty scan registers. We have introduced two solutions, based on the hardware and software, to test the reconfigurable scan network, to identify faulty scan registers, and repair the network by excluding the faulty scan register from the network. We did two experiments to measure the overhead in terms of area and data. Here, the data overhead is the data needed to be sent to IC for testing and repairing the reconfigurable network. From these experiments, we found both the solutions have unique advantages. The software solution does not use hardware area, while the hardware solution results in low data overhead.}},
author = {{Xiang, Zehang}},
language = {{eng}},
note = {{Student Paper}},
title = {{Test and Repair of Reconfigurable On-chip Instrument Access Networks}},
year = {{2019}},
}