A design of a 100 MS/s, 8-bit Pipelined ADC in CMOS
(2021) EITM02 20211Department of Electrical and Information Technology
- Abstract
- The thesis focuses on designing and simulating an 8-bit high-speed fully differential pipelined Analog to Digital Converter (ADC) in the 65nm Complementary Metal-Oxide-Semiconductor (CMOS) technology by using the software Cadence Virtuoso. The aim is to increase the operation speed of the ADC for communication systems without reducing the performance, in the meantime, the low power consumption and the low complexity should also be required when considering future implementation. The ADC works on 200mV to 800mV with 1.2V supply voltage and consists of six 1.5-bit stages, one 2-bit stage, and a series of digital correction circuits in the end. A Flash ADC, and a Multiplying Digital to Analogue Converter (MDAC) have been designed for each... (More)
- The thesis focuses on designing and simulating an 8-bit high-speed fully differential pipelined Analog to Digital Converter (ADC) in the 65nm Complementary Metal-Oxide-Semiconductor (CMOS) technology by using the software Cadence Virtuoso. The aim is to increase the operation speed of the ADC for communication systems without reducing the performance, in the meantime, the low power consumption and the low complexity should also be required when considering future implementation. The ADC works on 200mV to 800mV with 1.2V supply voltage and consists of six 1.5-bit stages, one 2-bit stage, and a series of digital correction circuits in the end. A Flash ADC, and a Multiplying Digital to Analogue Converter (MDAC) have been designed for each 1.5-bit stage, while the MDAC is not included in the 2-bit stage. SHA is designed at the beginning but not included in the final schematic since the sampling function is included in the MADC and the Flash ADC. The design also includes a bootstrapped switch to increase the linearity of the switches, a dynamic latch comparator to increase the speed of the Flash ADC, and a fully differential Operational Amplifier (OpAmp) to reduce the impact of the external noise, decrease the second-order harmonic distortion and increase the dynamic range. Simulation results illustrate the SNDR reaches 48.64dB when the sampling rate is 100MHz, and it remains 47.3dB when the sampling rate increases to 200MHz. (Less)
- Popular Abstract
- In the integrated circuit field, the Analog to Digital Converter (ADC) is used to convert the analog signals to binary digital signals. I will let you know why it is important, and I will start with a background introduction. Nowadays, with the rapid development of electronic technology, we can see electronic devices everywhere, which brings convenience and enriches our lives. The core of all the electron devices is a processor, which can be regarded as the brain created by integrated circuits. This brain is only using binary digital signals to do complex calculations. The binary number only includes 0 and 1, which build a complex digital world. However, the real world is analog, it requires a translator to translate the analog signals in... (More)
- In the integrated circuit field, the Analog to Digital Converter (ADC) is used to convert the analog signals to binary digital signals. I will let you know why it is important, and I will start with a background introduction. Nowadays, with the rapid development of electronic technology, we can see electronic devices everywhere, which brings convenience and enriches our lives. The core of all the electron devices is a processor, which can be regarded as the brain created by integrated circuits. This brain is only using binary digital signals to do complex calculations. The binary number only includes 0 and 1, which build a complex digital world. However, the real world is analog, it requires a translator to translate the analog signals in our real world to the digital signals in the digital world. That translator is the ADC, it is used in most electronic devices. For example, when we are using a mobile phone, our voice is an analog signal, the ADC converts it into a digital signal, then the mobile phone can recognize it and use it to realize different functions and applications. Without the ADC, most of the electronic devices in our life will stop working. The high-speed and high quality of the ADC is important to electronic devices. And my thesis focus on designing a high-speed 8-bit pipelined ADC. I will explain this title step by step. The speed of the ADC is called sampling rate, which represents how fast the ADC can sample the analog signals and convert them into digital signals. Usually, a sampling rate higher can 10MHz can be regarded as high-speed, and my ADC reaches 200MHz without conspicuous degrade of performance. 8-bit is the resolution of my ADC, it shows how accurate the ADC can be. For an 8-bit ADC, the analog signals are divided into 256 levels, and each of them is corresponding to a binary code. The pipelined structure is the key for the ADC can reach high-speed and high quality at the same time. Imagining the pipelined ADC is a large factory that includes several machines, and each machine process part of the material and gets some semi-finished products, and then sends them to the next machine until the end. Finally, all these semi-finished products are collected and processed to become final products. Here, the material is the analog input signal, and the product is the digital 3
output signal. These machines are the stages in the ADC, using more stages can increase the accuracy but also increase the delay, and vice versa. The performance is highly dependent on the technology that is using in the integrated circuit. The technology is limited by the accuracy of the stepper, which is used to fabricate the integrated circuits. For example, the technology of this design is 65nm, which means the maximum error in this integrated circuit is ±65nm. With the development of the steppers, this value will decrease gradually. I am looking forward to improving the design with higher technology in the future, it is exciting but also challenging. (Less)
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/student-papers/record/9055465
- author
- Zhang, Shen LU
- supervisor
- organization
- course
- EITM02 20211
- year
- 2021
- type
- H2 - Master's Degree (Two Years)
- subject
- report number
- LU/LTH-EIT 2021-814
- language
- English
- id
- 9055465
- date added to LUP
- 2021-06-17 14:07:28
- date last changed
- 2021-06-17 14:07:28
@misc{9055465,
abstract = {{The thesis focuses on designing and simulating an 8-bit high-speed fully differential pipelined Analog to Digital Converter (ADC) in the 65nm Complementary Metal-Oxide-Semiconductor (CMOS) technology by using the software Cadence Virtuoso. The aim is to increase the operation speed of the ADC for communication systems without reducing the performance, in the meantime, the low power consumption and the low complexity should also be required when considering future implementation. The ADC works on 200mV to 800mV with 1.2V supply voltage and consists of six 1.5-bit stages, one 2-bit stage, and a series of digital correction circuits in the end. A Flash ADC, and a Multiplying Digital to Analogue Converter (MDAC) have been designed for each 1.5-bit stage, while the MDAC is not included in the 2-bit stage. SHA is designed at the beginning but not included in the final schematic since the sampling function is included in the MADC and the Flash ADC. The design also includes a bootstrapped switch to increase the linearity of the switches, a dynamic latch comparator to increase the speed of the Flash ADC, and a fully differential Operational Amplifier (OpAmp) to reduce the impact of the external noise, decrease the second-order harmonic distortion and increase the dynamic range. Simulation results illustrate the SNDR reaches 48.64dB when the sampling rate is 100MHz, and it remains 47.3dB when the sampling rate increases to 200MHz.}},
author = {{Zhang, Shen}},
language = {{eng}},
note = {{Student Paper}},
title = {{A design of a 100 MS/s, 8-bit Pipelined ADC in CMOS}},
year = {{2021}},
}