Configurable, scalable single-ended sense amplifier with additional auxiliary blocks for low-power two-port memories in advanced FinFET technologies

Abstract

System on Chip (SoC) designs contain a variety of Intellectual Property (IP) cores, including digital signal processing blocks, media and graphics processing units, as well as processing core units that employ multiple-port memories to enhance performance and bandwidth. These memories allow parallel read/write operations from the same memory blocks from different ports. Due to the enormous number of on-chip memories in modern SoCs, area efficiency is critical. Going down the technology node of transistors to create these memories is one solution to reduce the area and increase the computational density. However, as transistors were continuously scaled-down, lesser gate control and higher leakage current became a major concern. This led the semiconductor industry to reinvent the underlying transistor architecture and manufacturing processes. Today, Fin Field Effect Transistor (FinFET) are the world’s pioneering transistors commercially available in the market. These are multigate transistors designed primarily for high-speed/high-density applications, that could effectively increase gate control.

In addition to area and power constraints, improving access time has always been a challenge in memories. Sense amplifiers are read circuit elements that are employed to interpret data bit stored in memory by amplifying a low-power bit line signal to recognizable logic levels, thereby improving the read access time. The goal of this thesis project is to use state-of-the-art finFET technology to design a low-power, configurable and compiler-friendly single-ended sense amplifier that can be easily scaled up or down based on the size of the memory block. This design dynamically produces reference voltage based on charge redistribution from high bit-line capacitance to low capacitance nodes. Apart from the single-ended sense amplifier, other memory sub-blocks like D Flip-flop, multiplexer and differential sense amplifier was also designed.

The designed circuits also had to be verified before and after the layout phase, to understand the effects of parasitics in the design. The design verification flow was automized using a python script that performs statistical analysis on transistor parameter variations and accumulates the results of the simulation tests and evaluates the failure probability. The thesis project was carried out in Xenergic AB.

Popular Abstract

Recent trends witness the size of semiconductor chips decrease to a few nanometers. Downscaling the process node allows for an increasing curve of computation density and also reducing the area. Owing to their structure, finFETs generate lower leakage power and provide for a more compact design. They also operate at a lower voltage and offer a high drive current. This means that much more performance can be packed into a smaller area and in turn reducing costs per unit performance.

Present-day SoCs feature multiple embedded processors, memory subsystems, and application-specific peripherals. Rather than relying on off-chip memory communication with limited inputs and outputs (I/Os) to exchange data, large memories are integrated into the chips themselves to prevent high look-up latencies. System power and performance of embedded SoCs are heavily influenced by their memory architecture. Back-to-back data processing requests in multi-core processing and multimedia applications demanded multi-port memories. Integration of additional bit lines and word lines lead to a massive area expense. Reducing area
and power overhead consumed by memory is a primary concern in SoC design.

With the ongoing research in this field, several methods are used to reduce power consumption in memories. One of the primary methods opted is to reduce the supply voltage. Alternatively, special read circuitry called sense amplifiers were proposed which reduces signal swing on bit lines thereby eliminating power dissipation due to charging and discharging. Sense amplifiers not only minimized power consumption to a greater extent but also enhanced the read performance
by minimizing sensing delay. This is done mainly by detecting and accelerating small bit line transitions. The sense amplifier’s design strongly influences memory
reliability (endurance, retention) and performance (access time).

The goal of this research project to design peripheral blocks for two port memories with a focus on configurable, compiler-friendly, scalable single-ended
sense amplifier using the latest finFET technology. The proposed single-ended sense amplifier design tactfully uses the parasitic bit line capacitances to act as
a source for generation of reference voltage during read operation. Additionally, the configurable property of the design reduces the area cost which could have,
otherwise, incurred in establishing dummy bit line columns. The thesis project mainly aims at achieving high-performance speed, high sensitivity, lower area, and
lesser power consumption at a system level.

• author: Subbaiah Kumar Nangaru, Limitha
• supervisor: Baktash Behmanesh
• organization: Department of Electrical and Information Technology
• course: EITM02 20221
• year: 2022
• type: H2 - Master's Degree (Two Years)
• subject: Technology and Engineering
• keywords: CMOS (Complementary Metal Oxide Semiconductors), DRC (Design Rule Check), Process Corners, FinFET (Fin Field Effect Transistor), IC (Integrated Circuit), LVS (Layout Versus Schematic), Monte Carlo, Nominal Voltage, PDK (Process Design Kit), Power Delay Product, Read Bit Line, Read Word Line, SoC (System on Chip), SRAM (Static Random Access Memory), Threshold Voltage
• report number: LU/LTH-EIT 2022-893
• language: English
• id: 9101389
• date added to LUP: 2022-10-10 14:02:02
• date last changed: 2022-10-10 14:02:02