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Testing Platform for Memory IPs using PULPissimo

Pabbisetty, Adithya Saikrishna LU (2022) EITM02 20221
Department of Electrical and Information Technology
Abstract
Memory IPs are important components in SoC designs. Hence, making sure that the memory IPs are functioning as expected is crucial for any organization. In order to do so, memory IPs must be tested. In addition, the testing capabilities can be enhanced by integrating a processor to the memory test chip. In this project, an open-source PULPissimo platform based on RISC-V ISA(Instruction set architecture) is used as this gives freedom to the system designer and the organization to configure the processor core as per the requirements. Further in this project, various checksum algorithms such as MD5, SHA-1 and SHA-256 are implemented in RTL which can be used to test the organization’s ROM IPs. Subsequently, each of the algorithms are integrated... (More)
Memory IPs are important components in SoC designs. Hence, making sure that the memory IPs are functioning as expected is crucial for any organization. In order to do so, memory IPs must be tested. In addition, the testing capabilities can be enhanced by integrating a processor to the memory test chip. In this project, an open-source PULPissimo platform based on RISC-V ISA(Instruction set architecture) is used as this gives freedom to the system designer and the organization to configure the processor core as per the requirements. Further in this project, various checksum algorithms such as MD5, SHA-1 and SHA-256 are implemented in RTL which can be used to test the organization’s ROM IPs. Subsequently, each of the algorithms are integrated to the PULPissimo to provide a platform for testing the ROM IPs. Finally, various comparisons are made using synthesized results. The three implemented algorithms are compared with respect to the number of gates used and latency to identify the suitable algorithm for the organization. Similarly, the cores in the PULPissimo are also compared to identify the preferable core to be used by the organization. (Less)
Popular Abstract
21st century is a new chapter in human development enabled by extraordinary technology advances. The speed, breadth and depth of these advancements demand the organizations to create value. In the domain of semiconductor industries, advances in technology have had a massive impact with numerous electronic devices. According to Moore’s law, the number of transistors on a chip doubles every two years. This has made drastic increase in cost per unit area while delivering a lot more functionality within that area. A large portion of the silicon area of many digital designs is dedicated to the storage of data. More than half of the transistors in today’s designs are devoted to memories and this ratio is expected to increase further. Hence,... (More)
21st century is a new chapter in human development enabled by extraordinary technology advances. The speed, breadth and depth of these advancements demand the organizations to create value. In the domain of semiconductor industries, advances in technology have had a massive impact with numerous electronic devices. According to Moore’s law, the number of transistors on a chip doubles every two years. This has made drastic increase in cost per unit area while delivering a lot more functionality within that area. A large portion of the silicon area of many digital designs is dedicated to the storage of data. More than half of the transistors in today’s designs are devoted to memories and this ratio is expected to increase further. Hence, memories are very important and crucial components to store data in the chips. To ensure their functionality and reliability, they need to be tested and verified thoroughly.

Electronic memories come in many different formats and sizes. They are most often classified as read-only (ROM) and read-write (RWM) memories based on memory functionality. The RWM structures have the advantage of offering both read and write functionality. Whereas ROMs are encoded and hardwired with data that cannot be modified. Among the various testing techniques, MBIST is the most popular one used by the organizations. However, MBIST algorithms include steps which involve writing and reading. Hence, they are mostly suited for read-write memories. Read-only memories, on the other hand, are tested for bit functionality using various algorithms like checksum.

In this project, three checksum algorithms namely MD5, SHA-1 and SHA-256 were implemented to test the bit functionality of ROMs. In addition, these algorithms were implemented in such a way that they could test any size of ROM. Further, these algorithms were compared with respect to various parameters such as area used and time taken to test the ROM. As a result of this comparison, MD5 was chosen as it uses less area and also less time to verify. To further improve the testing capabilities, a testing platform was considered for integrating the developed algorithm modules. In this project, PULPissimo platform which is an open-source platform was used to test the memories. Finally, the outcome of this project provides a testing platform for the organization to test their memories. (Less)
Please use this url to cite or link to this publication:
author
Pabbisetty, Adithya Saikrishna LU
supervisor
organization
course
EITM02 20221
year
type
H2 - Master's Degree (Two Years)
subject
report number
LU/LTH-EIT 2022-895
language
English
id
9101906
date added to LUP
2022-10-27 09:33:50
date last changed
2022-10-27 09:33:50
@misc{9101906,
  abstract     = {{Memory IPs are important components in SoC designs. Hence, making sure that the memory IPs are functioning as expected is crucial for any organization. In order to do so, memory IPs must be tested. In addition, the testing capabilities can be enhanced by integrating a processor to the memory test chip. In this project, an open-source PULPissimo platform based on RISC-V ISA(Instruction set architecture) is used as this gives freedom to the system designer and the organization to configure the processor core as per the requirements. Further in this project, various checksum algorithms such as MD5, SHA-1 and SHA-256 are implemented in RTL which can be used to test the organization’s ROM IPs. Subsequently, each of the algorithms are integrated to the PULPissimo to provide a platform for testing the ROM IPs. Finally, various comparisons are made using synthesized results. The three implemented algorithms are compared with respect to the number of gates used and latency to identify the suitable algorithm for the organization. Similarly, the cores in the PULPissimo are also compared to identify the preferable core to be used by the organization.}},
  author       = {{Pabbisetty, Adithya Saikrishna}},
  language     = {{eng}},
  note         = {{Student Paper}},
  title        = {{Testing Platform for Memory IPs using PULPissimo}},
  year         = {{2022}},
}