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- 2022
-
Mark
Efficient High-level Synthesis Implementation of massive MIMO Processing on RFSoC
(
- Master (Two yrs)
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Mark
FPGA Implementation of the ORB Algorithm
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- Master (Two yrs)
-
Mark
A Digital Design Flow - From Concept to RTL Description, Using Mathworks and Cadence's Tools
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- Master (Two yrs)
-
Mark
Testing Platform for Memory IPs using PULPissimo
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- Master (Two yrs)
- 2021
-
Mark
Investigation of dynamic control ML algorithms on existing and future Arm microNPU systems
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- Master (Two yrs)
-
Mark
Energy efficient Ericsson Many-Core Architecture (EMCA) IP blocks for 5G ASIC
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- Master (Two yrs)
-
Mark
Ethernet DMA Datapath Performance Optimization for 5G Radios
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- Master (Two yrs)
- 2020
-
Mark
Design and implementation of testable fault-tolerant RISC-V system
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- Master (Two yrs)
- 2019
-
Mark
Robust header compression for cellular IoT
(
- Master (Two yrs)