Design and Modeling of InxGa(1−x)As/InP based Nanosheet Field Effect Transistors for High Frequency Applications
(2023) EITM02 20221Department of Electrical and Information Technology
- Abstract
- The advancement of CMOS technology has been fueled by the need to satisfy Moore’s law by shrinking transistors to progressively smaller sizes and increasing the transistor density per unit area [1]. The dimension of the state-of-the-art MOSFET is now down to a few nanometers. However, with continued device scaling, the performance of Integrated Chips (ICs) starts to deteriorate, making it essential to implement novel technology solutions. The novel technologies, such as reshaping the devices’ geometries in [2], achieved better excellent electrostatic performance than planar technologies. For example, 3D finFETs or tri-gate architectures showed improved electrostatic control and necessitated further scaling of the transistor length.... (More)
- The advancement of CMOS technology has been fueled by the need to satisfy Moore’s law by shrinking transistors to progressively smaller sizes and increasing the transistor density per unit area [1]. The dimension of the state-of-the-art MOSFET is now down to a few nanometers. However, with continued device scaling, the performance of Integrated Chips (ICs) starts to deteriorate, making it essential to implement novel technology solutions. The novel technologies, such as reshaping the devices’ geometries in [2], achieved better excellent electrostatic performance than planar technologies. For example, 3D finFETs or tri-gate architectures showed improved electrostatic control and necessitated further scaling of the transistor length. Nanosheet FETs showed higher drive currents than FinFET technology at a given fin pitch and can further provide gate length scaling [3]. The geometry of the nanosheets allows all-around gate contact offering excellent electrostatic integrity. Power dissipation in CMOS applications is getting worse due to aggressive scaling [4]. One can overcome this by adding material to the channel with higher transport qualities, such as InGaAs [5]. The higher carrier mobility compared to Si enables high current at low operating voltages.
In this thesis, InGaAs nanosheet FETs high-frequency performance is investigated. The wider and thinner nanosheets are considered for analysis and are modeled with quasi 2D ballistic model. The device's extrinsic part, such as extrinsic capacitance, is modeled using electrostatic model in COMSOL. The intrinsic and extrinsic parts are combined, and the high-frequency metrics such as transition frequency, f_{T}, and the oscillation frequency, f_{max}, are evaluated. The device is optimised in terms of nanosheet width, thickness, separation between two stacks, source/drain spacer distance, the number of stacked channels and the composition of the material are optimized to get the best performance. (Less) - Popular Abstract
- The continuous improvement of electronic devices is limited by certain challenges. One such challenge is the emergence of short channel effects when scaling down the size of device channels [1]. However, a new type of transistor called FinFET shows promise in overcoming these limitations. FinFETs have a thin body and superior scalability due to gate control on the channel from three sides. They offer better electrostatics, lower power consumption, and higher performance compared to traditional planar bulk metal oxide semiconductor field effect transistors (MOSFETs). In recent studies, researchers have successfully achieved a better performance by integrating a new material layer into the conventional high-k metal gate process [6]. However,... (More)
- The continuous improvement of electronic devices is limited by certain challenges. One such challenge is the emergence of short channel effects when scaling down the size of device channels [1]. However, a new type of transistor called FinFET shows promise in overcoming these limitations. FinFETs have a thin body and superior scalability due to gate control on the channel from three sides. They offer better electrostatics, lower power consumption, and higher performance compared to traditional planar bulk metal oxide semiconductor field effect transistors (MOSFETs). In recent studies, researchers have successfully achieved a better performance by integrating a new material layer into the conventional high-k metal gate process [6]. However, FinFETs face challenges in terms of patterning, device performance, layout, and cost for further scaling [1]. As device pitches decrease, thinner and taller fin structures are required, which raises concerns for both performance and manufacturing processes.
To address these challenges, nanowire structures are being considered as a potential solution [7]. Nanowires offer better short-channel control and higher current density, enabling further device scaling. One limitation is their lower drive currents due to the inherently smaller effective channel width. However, this can be compensated by stacking several nanowires vertically. Recently, nanosheet field effect transistors (NSFETs) have been proposed as a continuation of device scaling [8]. In nanosheets, the width of the silicon body is not limited by fin pitch and quantization, allowing for more flexibility in achieving the desired effective channel width. The sheet-to-sheet spacing in nanosheets is determined by epitaxial processes, unlike the lithographically controlled fin pitch in FinFETs [6]. Moreover, multiple sheets can be stacked in the vertical direction to achieve the desired effective width per footprint.
Nanosheet structures have the superior gate control, lower mismatch in sub-threshold swing and drain-induced barrier lowering, and better frequency response. They also offer better flexibility to self-heating effects. However, NSFETs may require more complex modeling designs compared to FinFETs. This research aims to determine the optimal parameters and explore potential avenues for improvement based on NSFETs. (Less)
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/student-papers/record/9118982
- author
- Liu, Hanyu LU and Chen, Xi LU
- supervisor
- organization
- course
- EITM02 20221
- year
- 2023
- type
- H2 - Master's Degree (Two Years)
- subject
- keywords
- nanosheet (NS), gate-all-around (GAA), channel release, parasitic channel, MATLAB, COMSOL, technology node
- report number
- LU/LTH-EIT 2023-932
- language
- English
- id
- 9118982
- date added to LUP
- 2023-06-21 13:32:21
- date last changed
- 2023-06-26 11:49:10
@misc{9118982,
abstract = {{The advancement of CMOS technology has been fueled by the need to satisfy Moore’s law by shrinking transistors to progressively smaller sizes and increasing the transistor density per unit area [1]. The dimension of the state-of-the-art MOSFET is now down to a few nanometers. However, with continued device scaling, the performance of Integrated Chips (ICs) starts to deteriorate, making it essential to implement novel technology solutions. The novel technologies, such as reshaping the devices’ geometries in [2], achieved better excellent electrostatic performance than planar technologies. For example, 3D finFETs or tri-gate architectures showed improved electrostatic control and necessitated further scaling of the transistor length. Nanosheet FETs showed higher drive currents than FinFET technology at a given fin pitch and can further provide gate length scaling [3]. The geometry of the nanosheets allows all-around gate contact offering excellent electrostatic integrity. Power dissipation in CMOS applications is getting worse due to aggressive scaling [4]. One can overcome this by adding material to the channel with higher transport qualities, such as InGaAs [5]. The higher carrier mobility compared to Si enables high current at low operating voltages.
In this thesis, InGaAs nanosheet FETs high-frequency performance is investigated. The wider and thinner nanosheets are considered for analysis and are modeled with quasi 2D ballistic model. The device's extrinsic part, such as extrinsic capacitance, is modeled using electrostatic model in COMSOL. The intrinsic and extrinsic parts are combined, and the high-frequency metrics such as transition frequency, f_{T}, and the oscillation frequency, f_{max}, are evaluated. The device is optimised in terms of nanosheet width, thickness, separation between two stacks, source/drain spacer distance, the number of stacked channels and the composition of the material are optimized to get the best performance.}},
author = {{Liu, Hanyu and Chen, Xi}},
language = {{eng}},
note = {{Student Paper}},
title = {{Design and Modeling of InxGa(1−x)As/InP based Nanosheet Field Effect Transistors for High Frequency Applications}},
year = {{2023}},
}