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LUND UNIVERSITY LIBRARIES

A Digital Phase-Locked Loop for Frequency Synthesis using an Adaptive Pulse Shrinking TDC

Lewin, Viktor LU (2023) EITM01 20231
Department of Electrical and Information Technology
Abstract
This thesis investigates a new type of Phase-Locked Loop (PLL) architecture which combines a phase/frequency detector (PFD) and a digital loop filter. The quantization is done by a time-to-digital converter which continuously shrinks the pulse coming from the PFD and registers how far it propagates. Based on how far into the TDC each pulse propagates, the phase error is determined. The design is focused on the PFD and TDC at a reference frequency of 4 GHz, targeting output frequencies in the mmWave range. Advantages using this type of TDC include reduced power consumption and phase jitter as well as simplified digital processing logic and high reference frequencies.
The TDC has adjustable gain with its highest resolution less than 1... (More)
This thesis investigates a new type of Phase-Locked Loop (PLL) architecture which combines a phase/frequency detector (PFD) and a digital loop filter. The quantization is done by a time-to-digital converter which continuously shrinks the pulse coming from the PFD and registers how far it propagates. Based on how far into the TDC each pulse propagates, the phase error is determined. The design is focused on the PFD and TDC at a reference frequency of 4 GHz, targeting output frequencies in the mmWave range. Advantages using this type of TDC include reduced power consumption and phase jitter as well as simplified digital processing logic and high reference frequencies.
The TDC has adjustable gain with its highest resolution less than 1 picosecond. By using an adaptive PFD, the width of the output pulses is made adjustable. Using this feature, the number of active stages in the TDC can be adjusted to account for corner variation while also reducing power consumption and phase noise. The PFD and TDC together consumes around 2.1 mW of power at 4 GHz, with phase jitter of less than 30 fs. (Less)
Please use this url to cite or link to this publication:
author
Lewin, Viktor LU
supervisor
organization
course
EITM01 20231
year
type
H2 - Master's Degree (Two Years)
subject
keywords
Phase-locked loop, PLL, DPLL, Frequency Synthesis, TDC, PFD
report number
LU/LTH-EIT 2023-919
language
English
id
9128268
date added to LUP
2023-06-21 09:17:50
date last changed
2023-06-21 09:17:50
@misc{9128268,
  abstract     = {{This thesis investigates a new type of Phase-Locked Loop (PLL) architecture which combines a phase/frequency detector (PFD) and a digital loop filter. The quantization is done by a time-to-digital converter which continuously shrinks the pulse coming from the PFD and registers how far it propagates. Based on how far into the TDC each pulse propagates, the phase error is determined. The design is focused on the PFD and TDC at a reference frequency of 4 GHz, targeting output frequencies in the mmWave range. Advantages using this type of TDC include reduced power consumption and phase jitter as well as simplified digital processing logic and high reference frequencies.
The TDC has adjustable gain with its highest resolution less than 1 picosecond. By using an adaptive PFD, the width of the output pulses is made adjustable. Using this feature, the number of active stages in the TDC can be adjusted to account for corner variation while also reducing power consumption and phase noise. The PFD and TDC together consumes around 2.1 mW of power at 4 GHz, with phase jitter of less than 30 fs.}},
  author       = {{Lewin, Viktor}},
  language     = {{eng}},
  note         = {{Student Paper}},
  title        = {{A Digital Phase-Locked Loop for Frequency Synthesis using an Adaptive Pulse Shrinking TDC}},
  year         = {{2023}},
}