Skip to main content

LUP Student Papers

LUND UNIVERSITY LIBRARIES

Design of a 13-Bit SAR ADC with kT/C noise cancellation technique

Keerthy Kumar, Shashank LU (2023) EITM02 20232
Department of Electrical and Information Technology
Abstract
One of the main limitations of a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) is the large input capacitance needed to achieve the desired performance. This large input capacitance increases the total area of the ADC and it imposes the use of a powerful buffer to drive it. Since the input capacitance is inversely proportional to the kT/C noise, reducing it, generates more noise. To reduce the input capacitance, there is a need to deal with the extra noise generated.

In this thesis, a 13-bit SAR ADC at 40MS/s using kT/C noise cancellation has been designed in 65nm technology node. This technique allows for a considerable decrease in the size of the ADC input capacitor without reducing the ADC’s performance,... (More)
One of the main limitations of a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) is the large input capacitance needed to achieve the desired performance. This large input capacitance increases the total area of the ADC and it imposes the use of a powerful buffer to drive it. Since the input capacitance is inversely proportional to the kT/C noise, reducing it, generates more noise. To reduce the input capacitance, there is a need to deal with the extra noise generated.

In this thesis, a 13-bit SAR ADC at 40MS/s using kT/C noise cancellation has been designed in 65nm technology node. This technique allows for a considerable decrease in the size of the ADC input capacitor without reducing the ADC’s performance, it also reduces the requirements for the
input buffers. The designed SAR ADC uses a total input capacitance of 172.8 fF and it achieves an SNR of 67.64 dB before noise cancellation and 74.173 dB
after noise cancellation. To achieve similar results without implementing the noise cancellation technique one has to increase the input capacitance by at least 10 times. Hence, there is a need to implement noise cancellation techniques, as using large input capacitance to design SAR ADC increasing the overall area of the design. (Less)
Popular Abstract
With advancements in technology and integrated circuits, communication has evolved from telegraphs and landlines to video calls spanning the globe. There is a huge transition from large desktop computers to palm-sized mobile phones and tablets , emphasizing the pursuit of faster, more power efficient devices with increased memory capacity. At the core of all electronic devices is a processor, often called the brain of the computer operate using binary code (zeros and ones). But, the real world communicates in analog signals. To bridge this gap, ADCs are crucial, and present in nearly every electronic device. For instance, in a mobile phone, our voice, as an
analog signal, is converted by the ADC into a digital signal, enabling the device... (More)
With advancements in technology and integrated circuits, communication has evolved from telegraphs and landlines to video calls spanning the globe. There is a huge transition from large desktop computers to palm-sized mobile phones and tablets , emphasizing the pursuit of faster, more power efficient devices with increased memory capacity. At the core of all electronic devices is a processor, often called the brain of the computer operate using binary code (zeros and ones). But, the real world communicates in analog signals. To bridge this gap, ADCs are crucial, and present in nearly every electronic device. For instance, in a mobile phone, our voice, as an
analog signal, is converted by the ADC into a digital signal, enabling the device to recognize and utilize it for various functions and applications.

The thesis focuses on the design and implementation of a 13-bit Successive Approximation Register (SAR) ADC. Additionally, it aims to prove the effectiveness of the kT/C noise cancellation technique in reducing noise introduced during sampling. In this project, a 40 MHz sampling rate is employed for the 13-bit SAR ADC with kT/C noise cancellation. The resolution of the ADC set at 13 bits, indicates its accuracy, dividing analog signals into 8096 different levels, each corresponding to a binary code.

Designing a SAR ADC for higher bits requires a larger input capacitance. The challenge is to reduce this input capacitance while cancelling the resultant in kT/C noise generated, which would otherwise reduce the Signal-to-Noise Ratio (SNR) of the system. The implementation of the kT/C noise cancellation technique aims to address this challenge, allowing for the use of a smaller input capacitance while maintaining or improving the SNR. (Less)
Please use this url to cite or link to this publication:
author
Keerthy Kumar, Shashank LU
supervisor
organization
course
EITM02 20232
year
type
H2 - Master's Degree (Two Years)
subject
report number
LU/LTH-EIT 2023-958
language
English
id
9142088
date added to LUP
2023-12-07 12:35:49
date last changed
2023-12-07 12:35:49
@misc{9142088,
  abstract     = {{One of the main limitations of a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) is the large input capacitance needed to achieve the desired performance. This large input capacitance increases the total area of the ADC and it imposes the use of a powerful buffer to drive it. Since the input capacitance is inversely proportional to the kT/C noise, reducing it, generates more noise. To reduce the input capacitance, there is a need to deal with the extra noise generated.

In this thesis, a 13-bit SAR ADC at 40MS/s using kT/C noise cancellation has been designed in 65nm technology node. This technique allows for a considerable decrease in the size of the ADC input capacitor without reducing the ADC’s performance, it also reduces the requirements for the
input buffers. The designed SAR ADC uses a total input capacitance of 172.8 fF and it achieves an SNR of 67.64 dB before noise cancellation and 74.173 dB
after noise cancellation. To achieve similar results without implementing the noise cancellation technique one has to increase the input capacitance by at least 10 times. Hence, there is a need to implement noise cancellation techniques, as using large input capacitance to design SAR ADC increasing the overall area of the design.}},
  author       = {{Keerthy Kumar, Shashank}},
  language     = {{eng}},
  note         = {{Student Paper}},
  title        = {{Design of a 13-Bit SAR ADC with kT/C noise cancellation technique}},
  year         = {{2023}},
}