A Source-Follower Based Pipeline ADC Design with Error Correction
(2024) EITM02 20241Department of Electrical and Information Technology
- Abstract
- The content of this thesis consists of two parts, theoretical analysis of a pipeline
ADC mainly in terms of error source and correction and a source follower based
pipeline ADC design prototype.
For the general pipeline ADC analysis, we discuss the influence of typical
nonidealities from different building blocks, e.g. the comparator, residual amplifier,
and DAC, and show the corresponding treatments for these errors. We also discuss
the general background correction method using LMS algorithm to resolve gain,
memory effects and nonlinearities in the pipeline ADC analog part. For a high
speed and high accuracy pipeline ADC, one of the promising method is using open-
loop residual amplifier with complex linear and nonlinear... (More) - The content of this thesis consists of two parts, theoretical analysis of a pipeline
ADC mainly in terms of error source and correction and a source follower based
pipeline ADC design prototype.
For the general pipeline ADC analysis, we discuss the influence of typical
nonidealities from different building blocks, e.g. the comparator, residual amplifier,
and DAC, and show the corresponding treatments for these errors. We also discuss
the general background correction method using LMS algorithm to resolve gain,
memory effects and nonlinearities in the pipeline ADC analog part. For a high
speed and high accuracy pipeline ADC, one of the promising method is using open-
loop residual amplifier with complex linear and nonlinear correction. Nonlinear
correction can be especially costly in digital hardware. In this thesis, we evaluate a
new source-follower based architecture for the residual amplifier which has intrinsic
good linearity to avoid digital nonlinearity correction. We apply basic inter-stage
gain correction and memory effect correction in the software side to correct the
output data. The memory effect correction show great improvement which makes
it promising for high speed designs. The design is implemented in 7nm finFET
technology. In the typical process corner (tt), 80◦C, and 0.75 V power supply,
the circuit runs at 4 GHz clock frequency and 2 GHz signal frequency with SNDR
22.2 dB and SFDR 24.1 dB before correction. After gain and memory correction,
the performance is SNDR 58.8 dB and SFDR 77.7 dB. Especially, memory effect
correction shows an additional 11 dB improvement in SFDR. The average current
consumption is 20 mA, and the corresponding FoM is 167.3 dB. (Less) - Popular Abstract
- Nowadays, people are quite getting used to hear about "4G" or "5G". It actually
means 4th or 5th generation of wireless communication. The revolution from 4th
to 5th is basically high carrier frequency and larger bandwidth. People may wonder
what carrier frequency and bandwidth mean. If we take logistics as an example,
the information we transfer is the good. Higher carrier frequency is equal to faster
speed of the train, it will reduce the time used. Larger bandwidth is equal to
having more train carriages, it can transfer more information each time. Then
the analog to digital converter(ADC) we discussed in the thesis is like loading and
unloading along this good supply chain. It plays a role of interaction between
transferring... (More) - Nowadays, people are quite getting used to hear about "4G" or "5G". It actually
means 4th or 5th generation of wireless communication. The revolution from 4th
to 5th is basically high carrier frequency and larger bandwidth. People may wonder
what carrier frequency and bandwidth mean. If we take logistics as an example,
the information we transfer is the good. Higher carrier frequency is equal to faster
speed of the train, it will reduce the time used. Larger bandwidth is equal to
having more train carriages, it can transfer more information each time. Then
the analog to digital converter(ADC) we discussed in the thesis is like loading and
unloading along this good supply chain. It plays a role of interaction between
transferring and destination.
In reality, the function of ADC is to convert the analog signal into digital code.
It needs to be fast to keep up with speed of transferring as we mimicked above.
Another consideration is the linearity, which requires the converter output to be
as linear to the input as possible. We find that this linearity performance can
be impacted by some "fixed" errors. The mentioned "fixed" error is to distinguish
with "random" one. How to handle these errors is one of the key theory parts in
this thesis. Finally, we come up with the goal to design a high speed and high
linear ADC.
How to boost the speed is the first problem. Intuitively, we believe that simple
circuit form can have rather fast speed. The problem accompanied with high speed
benefit is the inaccuracy. This inaccuracy we encountered here is mainly for gain
factors inside the system, which is one major "fixed" error as we mentioned above.
To deal with this error it comes with the idea of "correction". The basic strategy
is that we try to "estimate" this error, and use the estimation value to recover the
correct data. Here how to estimate is a mature algorithm referred as least square
error.
Another finding is the hidden bandwidth limitation inside the ADC analog
circuit when the system runs at quite high speed. This limitation acts as a low
pass filtering and degrades the linearity performance. Intuitively, this low pass
filtering in the analog side can be compensated by having another high pass digital
filter in the digital part. The coefficients of digital filter can be estimated the same
way as gain error mentioned above. (Less)
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/student-papers/record/9161644
@misc{9161644,
abstract = {{The content of this thesis consists of two parts, theoretical analysis of a pipeline
ADC mainly in terms of error source and correction and a source follower based
pipeline ADC design prototype.
For the general pipeline ADC analysis, we discuss the influence of typical
nonidealities from different building blocks, e.g. the comparator, residual amplifier,
and DAC, and show the corresponding treatments for these errors. We also discuss
the general background correction method using LMS algorithm to resolve gain,
memory effects and nonlinearities in the pipeline ADC analog part. For a high
speed and high accuracy pipeline ADC, one of the promising method is using open-
loop residual amplifier with complex linear and nonlinear correction. Nonlinear
correction can be especially costly in digital hardware. In this thesis, we evaluate a
new source-follower based architecture for the residual amplifier which has intrinsic
good linearity to avoid digital nonlinearity correction. We apply basic inter-stage
gain correction and memory effect correction in the software side to correct the
output data. The memory effect correction show great improvement which makes
it promising for high speed designs. The design is implemented in 7nm finFET
technology. In the typical process corner (tt), 80◦C, and 0.75 V power supply,
the circuit runs at 4 GHz clock frequency and 2 GHz signal frequency with SNDR
22.2 dB and SFDR 24.1 dB before correction. After gain and memory correction,
the performance is SNDR 58.8 dB and SFDR 77.7 dB. Especially, memory effect
correction shows an additional 11 dB improvement in SFDR. The average current
consumption is 20 mA, and the corresponding FoM is 167.3 dB.}},
author = {{Li, Wenbo}},
language = {{eng}},
note = {{Student Paper}},
title = {{A Source-Follower Based Pipeline ADC Design with Error Correction}},
year = {{2024}},
}