Comparator Design for High Speed ADC

Abstract

High-speed Analog-to-Digital Converters (ADCs) play an important role in mod-
ern electronic systems, especially those systems that require high data rates and
low power consumption. These converters are essential components in various
applications, including telecommunications, medical imaging, radar systems, and
wireless communication.
This thesis explores four different dynamic comparators to enhance the speed
and efficiency for a 10-bit SAR-Pipeline ADC which is applied as 6 + 5 bits with
one redundant bit. It encounters critical challenges such as optimizing speed, min-
imizing input referred noise, and reducing power consumption. By using a 22nm
Fully-Depleted Silicon-On-Insulator (FDSOI) technology, this thesis involves de-
tailed pre-layout and post-layout simulations to ensure the robustness and relia-
bility of the comparator designs.
In pre-layout simulations, the triple-tail comparator with a feedforward path
shows the fastest decision time of 60pS, compared to 100pS for the strong-arm latch
and 80pS for the double-tail comparator. All the comparators in this thesis could
meet the requirements of input referred noise and kickback noise, both smaller
than half of LSB (Least Significant Bit). The post-layout results show that, while
it introduces some parasitics like capacitances and resistances that deteriorate
speed and kickback noise, it has a minimal impact on noise performance and
power consumption. The exploration for comparators provides valuable insights
into the design of high-speed ADCs. Future research directions include further
reducing noise and power consumption and integrating these comparators into
more complex systems for real-world applications.

Popular Abstract

There are continuous analog signals and discrete digital signals in our life. For
example, physical quantities in nature such as sound, temperature, and voltage
are usually analog signals. These signals are continuously changing and have no
discrete points in time. Digital signals are discrete signals whose amplitude can
only take on specific discrete values. The most common digital signals are binary
signals that can only take on the values 0 and 1. For example, the information
processed within a computer is a digital signal, and all data is stored and processed
in binary form.
An analog-to-digital converter (ADC) is a device that converts an analog signal
to a digital signal. ADCs are used in a wide variety of applications, including but
not limited to:
Audio and video equipment: Analog signals captured by microphones, video
cameras, and other devices are converted to digital signals by ADCs for digital
audio and video processing and storage.
Radar: Radar systems receive analog signals from the target through the an-
tenna, and the ADC is responsible for converting these analog signals into digital
form. This digitization allows the signal to be processed by digital systems, such
as computers, digital signal processors, etc.
And the role of the comparator is to determine whether something is big or
small. In an ADC, the job of the comparator is to compare the input analog signal
with a reference voltage. If the input signal is larger than the reference voltage,
the comparator outputs a high level, and if the input signal is smaller than the
reference voltage, the comparator outputs a low level. This output is what is used
to help the ADC determine the size of the input signal and then convert it to
digital form.
Comparators have many key properties that need to be investigated and con-
tinually improved, such as speed and noise. Speed refers to how fast the com-
parator can complete a comparison operation. In some applications, especially in
high-speed radar or communication systems, signals change very quickly, so the
comparator needs to be able to react at a very high speed or it will miss an impor-
tant part of the signal. So the speed performance of the comparator is studied to
ensure that it can perform the comparison operation in a very short time. Noise
refers to random fluctuations in the output of the comparator that introduce un-
certainty and affect the accuracy of the ADC. For instance, if the noise in the

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comparator output is too large, it will make the input signal not stable enough,
leading to errors in the conversion results. Therefore, the study of the noise per-
formance of the comparator is to ensure that its output is as accurate as possible
and is not disturbed by noise.
In this thesis, we investigated several different structures of comparators to im-
prove their performance for use in high-speed ADCs. During the investigation, we
encountered some challenges such as trade-off between speed and noise, difficulty
in establishing the correct test-bench circuit. Eventually, we successfully designed
four different comparators that meet the requirements of the system ADC and
compared their performance in a variety of ways.

• author: Yang, Chenguang
• supervisor: Baktash Behmanesh; Sunny Sharma; Hamidreza Ameri
• organization: Department of Electrical and Information Technology
• course: EITM02 20241
• year: 2024
• type: H2 - Master's Degree (Two Years)
• subject: Technology and Engineering
• report number: LU/LTH-EIT 2024-989
• language: English
• id: 9164380
• date added to LUP: 2024-06-17 14:15:58
• date last changed: 2024-06-17 14:15:58