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Architecture Exploration for Die-to-Die Communications

Georgiou, Pinelopi LU and Rao, Anshul LU (2024) EITM02 20241
Department of Electrical and Information Technology
Abstract
Novel circuit design and manufacturing methodologies are emerging into the market. Heterogeneous Integration allows for chiplet technologies of different process nodes to be combined
in one large package. To allow for seamless communication between them, a definition of standards is necessary, and so is the construction of interconnects that follow them. In this thesis,
we present an offload engine which bridges the popular System-On-Chip (SoC) communications standard, Advanced eXtensible Interface (AXI), with the evolving Universal Chiplet
Interconnect Express (UCIe). We dive into the details of the offload engine design process, the
challenges, and the novice methods used to connect the AXI protocol to the UCIe interface.
The... (More)
Novel circuit design and manufacturing methodologies are emerging into the market. Heterogeneous Integration allows for chiplet technologies of different process nodes to be combined
in one large package. To allow for seamless communication between them, a definition of standards is necessary, and so is the construction of interconnects that follow them. In this thesis,
we present an offload engine which bridges the popular System-On-Chip (SoC) communications standard, Advanced eXtensible Interface (AXI), with the evolving Universal Chiplet
Interconnect Express (UCIe). We dive into the details of the offload engine design process, the
challenges, and the novice methods used to connect the AXI protocol to the UCIe interface.
The resulting architecture is meant to be mounted in the Protocol Layer of the UCIe model.
Balancing complexity, latency, and size of the design we justify each decision that was taken
along the process. In this work, we also present future improvements which can be made to
the design. The result is an interface which may be used as part of a Die-to-Die interconnection, fully compatible with the UCIe standard. It may be the start of a commercial product
or provide insights into interconnection technologies. This work is relevant for designers and
researchers alike who wish to integrate their AXI-based architectures into a heterogeneous
package. (Less)
Popular Abstract
Novel circuit design and manufacturing methodologies are emerging into the market. Heterogeneous Integration allows for chiplet technologies of different process nodes to be combined
in one large package. To allow for seamless communication between them, a definition of standards is necessary, and so is the construction of interconnects that follow them. In this thesis,
we present an offload engine which bridges the popular System-On-Chip (SoC) communications standard, Advanced eXtensible Interface (AXI), with the evolving Universal Chiplet
Interconnect Express (UCIe). We dive into the details of the offload engine design process, the
challenges, and the novice methods used to connect the AXI protocol to the UCIe interface.
The... (More)
Novel circuit design and manufacturing methodologies are emerging into the market. Heterogeneous Integration allows for chiplet technologies of different process nodes to be combined
in one large package. To allow for seamless communication between them, a definition of standards is necessary, and so is the construction of interconnects that follow them. In this thesis,
we present an offload engine which bridges the popular System-On-Chip (SoC) communications standard, Advanced eXtensible Interface (AXI), with the evolving Universal Chiplet
Interconnect Express (UCIe). We dive into the details of the offload engine design process, the
challenges, and the novice methods used to connect the AXI protocol to the UCIe interface.
The resulting architecture is meant to be mounted in the Protocol Layer of the UCIe model.
Balancing complexity, latency, and size of the design we justify each decision that was taken
along the process. In this work, we also present future improvements which can be made to
the design. The result is an interface which may be used as part of a Die-to-Die interconnection, fully compatible with the UCIe standard. It may be the start of a commercial product
or provide insights into interconnection technologies. This work is relevant for designers and
researchers alike who wish to integrate their AXI-based architectures into a heterogeneous
package. (Less)
Please use this url to cite or link to this publication:
author
Georgiou, Pinelopi LU and Rao, Anshul LU
supervisor
organization
course
EITM02 20241
year
type
H2 - Master's Degree (Two Years)
subject
keywords
chiplet, UCIe, AXI, Die-to-Die, interconnect, heterogeneous integration, rtl design, dies, SoC, SiP, semiconductors, chip design, packaging
report number
LU/LTH-EIT 2024-1016
language
English
id
9175085
date added to LUP
2024-09-23 13:31:44
date last changed
2024-09-25 09:07:34
@misc{9175085,
  abstract     = {{Novel circuit design and manufacturing methodologies are emerging into the market. Heterogeneous Integration allows for chiplet technologies of different process nodes to be combined
in one large package. To allow for seamless communication between them, a definition of standards is necessary, and so is the construction of interconnects that follow them. In this thesis,
we present an offload engine which bridges the popular System-On-Chip (SoC) communications standard, Advanced eXtensible Interface (AXI), with the evolving Universal Chiplet
Interconnect Express (UCIe). We dive into the details of the offload engine design process, the
challenges, and the novice methods used to connect the AXI protocol to the UCIe interface.
The resulting architecture is meant to be mounted in the Protocol Layer of the UCIe model.
Balancing complexity, latency, and size of the design we justify each decision that was taken
along the process. In this work, we also present future improvements which can be made to
the design. The result is an interface which may be used as part of a Die-to-Die interconnection, fully compatible with the UCIe standard. It may be the start of a commercial product
or provide insights into interconnection technologies. This work is relevant for designers and
researchers alike who wish to integrate their AXI-based architectures into a heterogeneous
package.}},
  author       = {{Georgiou, Pinelopi and Rao, Anshul}},
  language     = {{eng}},
  note         = {{Student Paper}},
  title        = {{Architecture Exploration for Die-to-Die Communications}},
  year         = {{2024}},
}