On-chip Memory Power Optimization on Mobile GPU
(2024) EITM02 20241Department of Electrical and Information Technology
- Abstract
- High-performance mobile GPUs (Graphics Processing Units) handle complex graphics workloads, significantly benefiting the development of mobile gaming. However, the growing demand for enhanced GPU performance presents a major challenge in controlling power consumption, where memory usage plays a critical role. This thesis focuses on exploring methods to reduce power consumption in GPU Tile
Buffer memories within the Pixel Post-Processor (PPP). To achieve this, the thesis analyzes Tile Buffer memory access patterns and proposes a new approach: the Pre-Blender Merge Queue (PBMQ). The PBMQ, built before the Blender, reduces Tile Buffer memory access by merging multiple messages before they enter the Blender. Physical implementation results... (More) - High-performance mobile GPUs (Graphics Processing Units) handle complex graphics workloads, significantly benefiting the development of mobile gaming. However, the growing demand for enhanced GPU performance presents a major challenge in controlling power consumption, where memory usage plays a critical role. This thesis focuses on exploring methods to reduce power consumption in GPU Tile
Buffer memories within the Pixel Post-Processor (PPP). To achieve this, the thesis analyzes Tile Buffer memory access patterns and proposes a new approach: the Pre-Blender Merge Queue (PBMQ). The PBMQ, built before the Blender, reduces Tile Buffer memory access by merging multiple messages before they enter the Blender. Physical implementation results show that the PBMQ occupies only small percentage of the total PPP area after synthesis. Stress test results indicate that PBMQ reduces GPU processing time by 9% to 36% for different tasks, lowers Tile Buffer memory power consumption by 12% to 20%, and decreases overall PPP power consumption by 2% to 4%. (Less) - Popular Abstract
- GPUs (Graphics Processing Units) are specialized integrated circuits designed for extensive parallel computation, particularly to accelerate graphics processing. The development of mobile GPUs has greatly advanced smartphone capabilities, particularly for mobile gaming. However, the growing demand for higher mobile GPU performance presents a significant challenge in managing power consumption. Increasing scene complexity leads to a rise in memory accesses related to geometry, which in turn increases memory system power consumption.
Power dissipation in GPUs is typically categorized into dynamic and static power. Dynamic power is consumed when circuits are active and is proportional to network activity and switching frequency. Static... (More) - GPUs (Graphics Processing Units) are specialized integrated circuits designed for extensive parallel computation, particularly to accelerate graphics processing. The development of mobile GPUs has greatly advanced smartphone capabilities, particularly for mobile gaming. However, the growing demand for higher mobile GPU performance presents a significant challenge in managing power consumption. Increasing scene complexity leads to a rise in memory accesses related to geometry, which in turn increases memory system power consumption.
Power dissipation in GPUs is typically categorized into dynamic and static power. Dynamic power is consumed when circuits are active and is proportional to network activity and switching frequency. Static power, also known as leakage power, results from leakage currents through transistors. Modern Electronic Design Automation (EDA) tools offer support for estimating power consumption at the Register-Transfer Level (RTL).
This thesis analyzes Tile Buffer memory access patterns and introduces the Pre-Blender-Merge-Queue (PBMQ) to reduce power consumption in GPU Tile Buffer memories. The Tile Buffer, located within the Pixel Post-Processor (PPP), is responsible for receiving pixels, storing them in internal memories, and dispatching them as needed. PBMQ is positioned before the Blender and can reduce Tile Buffer memory access by merging multiple messages before they enter the Blender. This thesis successfully designs and implements the PBMQ algorithm and architecture in RTL, and integrates it into the GPU.
Physical synthesis results demonstrate that PBMQ occupies a minimal area compared to the overall PPP. Stress test results confirm PBMQ's contribution to performance improvement and power reduction. (Less)
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/student-papers/record/9175683
- author
- Yang, Zhiyuan LU
- supervisor
-
- Liang Liu LU
- organization
- alternative title
- Investigate Way to Reduce Power for GPU Tile Buffer RAM Access
- course
- EITM02 20241
- year
- 2024
- type
- H2 - Master's Degree (Two Years)
- subject
- keywords
- GPU, Tile Buffer RAM, Power reduction
- report number
- LU/LTH-EIT 2024-1018
- language
- English
- id
- 9175683
- date added to LUP
- 2024-10-09 10:00:14
- date last changed
- 2024-10-09 10:00:14
@misc{9175683,
abstract = {{High-performance mobile GPUs (Graphics Processing Units) handle complex graphics workloads, significantly benefiting the development of mobile gaming. However, the growing demand for enhanced GPU performance presents a major challenge in controlling power consumption, where memory usage plays a critical role. This thesis focuses on exploring methods to reduce power consumption in GPU Tile
Buffer memories within the Pixel Post-Processor (PPP). To achieve this, the thesis analyzes Tile Buffer memory access patterns and proposes a new approach: the Pre-Blender Merge Queue (PBMQ). The PBMQ, built before the Blender, reduces Tile Buffer memory access by merging multiple messages before they enter the Blender. Physical implementation results show that the PBMQ occupies only small percentage of the total PPP area after synthesis. Stress test results indicate that PBMQ reduces GPU processing time by 9% to 36% for different tasks, lowers Tile Buffer memory power consumption by 12% to 20%, and decreases overall PPP power consumption by 2% to 4%.}},
author = {{Yang, Zhiyuan}},
language = {{eng}},
note = {{Student Paper}},
title = {{On-chip Memory Power Optimization on Mobile GPU}},
year = {{2024}},
}