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LUND UNIVERSITY LIBRARIES

Investigation of Formal Verification Method for Clock and Reset Generation

Xi, Zhenzhong LU and Wang, Bin LU (2024) EITM02 20241
Department of Electrical and Information Technology
Abstract
Digital integrated circuits are fundamental to modern electronic devices, with increasing design complexity requiring robust verification methods to ensure error free functionality. This thesis examines the critical role of formal verification in digital Integrated Circuits (IC) design, particularly during the architecture modeling phase. Using a state machine module that controls clock frequency and reset signals as a case study, the paper outlines the key modeling steps and the complete formal verification process. The analysis of verification results, including coverage and runtime, highlights the strengths and limitations of the method. Additionally, a comparison between formal verification and simulation is provided, offering insights... (More)
Digital integrated circuits are fundamental to modern electronic devices, with increasing design complexity requiring robust verification methods to ensure error free functionality. This thesis examines the critical role of formal verification in digital Integrated Circuits (IC) design, particularly during the architecture modeling phase. Using a state machine module that controls clock frequency and reset signals as a case study, the paper outlines the key modeling steps and the complete formal verification process. The analysis of verification results, including coverage and runtime, highlights the strengths and limitations of the method. Additionally, a comparison between formal verification and simulation is provided, offering insights into the effectiveness of both approaches. (Less)
Please use this url to cite or link to this publication:
author
Xi, Zhenzhong LU and Wang, Bin LU
supervisor
organization
course
EITM02 20241
year
type
H2 - Master's Degree (Two Years)
subject
report number
LU/LTH-EIT 2024-1020
language
English
id
9176241
date added to LUP
2024-10-16 10:56:03
date last changed
2024-10-16 10:56:03
@misc{9176241,
  abstract     = {{Digital integrated circuits are fundamental to modern electronic devices, with increasing design complexity requiring robust verification methods to ensure error free functionality. This thesis examines the critical role of formal verification in digital Integrated Circuits (IC) design, particularly during the architecture modeling phase. Using a state machine module that controls clock frequency and reset signals as a case study, the paper outlines the key modeling steps and the complete formal verification process. The analysis of verification results, including coverage and runtime, highlights the strengths and limitations of the method. Additionally, a comparison between formal verification and simulation is provided, offering insights into the effectiveness of both approaches.}},
  author       = {{Xi, Zhenzhong and Wang, Bin}},
  language     = {{eng}},
  note         = {{Student Paper}},
  title        = {{Investigation of Formal Verification Method for Clock and Reset Generation}},
  year         = {{2024}},
}