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Optimizing FinFET Geometry using a Chemical Mechanical Polishing Process

Böhm, Paul LU (2025) EITM02 20251
Department of Electrical and Information Technology
Abstract
This paper aims to test the viability of using chemical mechanical polishing (CMP) in the manufacturing of vertical FinFET structures, and optimize the process parameters to this end. While the overarching goal is to facilitate production of gallium nitride FinFET structures for high-power applications through repeated employment of deposition and planarization with CMP, the process is initially validated with less costly silicon wafers. Using optical microscopy, ellipsometry, and atomic force microscopy (AFM), Si samples deposited with Al$_2$O$_3$ and SiO$_2$ are analyzed after processing in the CMP. Low overall sample defects were observed using low carrier and plate rotational speeds and sufficient slurry flow rates. Analysis of... (More)
This paper aims to test the viability of using chemical mechanical polishing (CMP) in the manufacturing of vertical FinFET structures, and optimize the process parameters to this end. While the overarching goal is to facilitate production of gallium nitride FinFET structures for high-power applications through repeated employment of deposition and planarization with CMP, the process is initially validated with less costly silicon wafers. Using optical microscopy, ellipsometry, and atomic force microscopy (AFM), Si samples deposited with Al$_2$O$_3$ and SiO$_2$ are analyzed after processing in the CMP. Low overall sample defects were observed using low carrier and plate rotational speeds and sufficient slurry flow rates. Analysis of non-patterned samples using ellipsometry revealed a non-uniformity in etch rate across the samples, regardless of carrier backpressure. The non-uniformity was mitigated when rotating the sample in the sample holder halfway through the CMP process, though this increased the rate of other defects. Patterned samples were found to suffer from dishing and uneven pattern etching. The most optimal configuration was positively patterned samples with a Cr layer under the oxide to enhance etching selectivity. Post CMP, a minimum pattern depth of about 20~nm was achieved with a global variation of about 10~nm due to non-uniformity, which is mostly acceptable for vertical high-power applications. Solvent cleaning and sonication proved insufficient in removing the particulates in slurry residue, highlighting the need for mechanical means of sample cleaning. Post-CMP surface roughness was found to be slightly higher in SiO$_2$ compared to Al$_2$O$_3$, and in general 12 to 35 percent higher than pre-CMP surfaces. (Less)
Popular Abstract
Polishing Electronics on the Nanometer Scale

The chemical mechanical polisher, commonly shortened to the initials CMP, is an important tool in the fabrication of modern day semiconductor devices. Using a large rotating plate and polishing fluid to grind down samples just a few atoms per second, the CMP is like a sanding machine with nanometer scale precision. The key to successfully polishing anything in the CMP is choosing the right parameters for the job. These parameters include the rotation speed of the plate, the pressure at which the sample is pressed down onto the plate, and how much polishing fluid is used. To see how effective the CMP is in fabricating modern semiconductors, different parameters are used to polish various test... (More)
Polishing Electronics on the Nanometer Scale

The chemical mechanical polisher, commonly shortened to the initials CMP, is an important tool in the fabrication of modern day semiconductor devices. Using a large rotating plate and polishing fluid to grind down samples just a few atoms per second, the CMP is like a sanding machine with nanometer scale precision. The key to successfully polishing anything in the CMP is choosing the right parameters for the job. These parameters include the rotation speed of the plate, the pressure at which the sample is pressed down onto the plate, and how much polishing fluid is used. To see how effective the CMP is in fabricating modern semiconductors, different parameters are used to polish various test samples.

Tweaking a parameter can effect the sample in many different ways, so finding the right ones is usually a balancing act. To gauge the success of a polishing process, the surface of the sample needs to be analyzed on the nanometer scale. This is achieved by using advanced microscopy techniques such as atomic force microscopy, which can reconstruct the surface of the sample by probing it with a very thin needle. Some important factors in determining the success of a run are how flat the surface is, how clean it is, and how rough it is after polishing in the CMP.

As a highly versatile tool, the CMP can be used in the fabrication of many different semiconductor devices. However, the device in focus for this thesis is the so-called FinFET, being a field-effect-transistors named after its fin-like shape. The FinFET is a fairly recent innovation in the pursuit of shrinking transistors to ever smaller dimensions, showing promising results. Due to its iconic vertical fin and small size, it can be somewhat tricky to fabricate with conventional means, a challenge the CMP hopes to overcome. With good parameters, the CMP can polish a surface flat and smooth enough to allow for parts of the FinFET to be built in multiple overlapping layers.

This thesis aimed to test the viability of using the CMP in the fabrication of FinFETs by polishing plain and patterned samples and finding the optimal parameters for the job. We found that slower rotational speeds in the CMP resulted in less samples breaking or having defects when enough polishing fluid was present. The surface turned out to be slightly rougher after polishing, and somewhat uneven across the whole sample. One end of the sample might end up being around 10 to 20 nanometers higher than the other, which can complicate things.

A good polishing procedure for patterned samples was achieved when adding a thin layer of chromium under the main layer, making it easier to polish only up to a certain target depth. Although the samples are cleaned afterwards using chemicals, the polishing fluid still left behind some persistent residue. For future experiments, we recommend using additional mechanical methods of cleaning like scrubbing or wiping the samples to get rid of this residue. (Less)
Please use this url to cite or link to this publication:
author
Böhm, Paul LU
supervisor
organization
course
EITM02 20251
year
type
H2 - Master's Degree (Two Years)
subject
keywords
CMP, chemical mechanical polishing, backpressure, sample defects, defects, planarization, fabrication, FinFET, vertical transistor, power electronics, non-uniformity, ellipsometry, AFM, atomic force microscopy, ALD. atomic layer deposition, patterned sample, roughness, cleanliness, selectivity
report number
LU/LTH-EIT 2025-1059
language
English
id
9194467
date added to LUP
2025-06-16 14:27:07
date last changed
2025-06-16 14:27:07
@misc{9194467,
  abstract     = {{This paper aims to test the viability of using chemical mechanical polishing (CMP) in the manufacturing of vertical FinFET structures, and optimize the process parameters to this end. While the overarching goal is to facilitate production of gallium nitride FinFET structures for high-power applications through repeated employment of deposition and planarization with CMP, the process is initially validated with less costly silicon wafers. Using optical microscopy, ellipsometry, and atomic force microscopy (AFM), Si samples deposited with Al$_2$O$_3$ and SiO$_2$ are analyzed after processing in the CMP. Low overall sample defects were observed using low carrier and plate rotational speeds and sufficient slurry flow rates. Analysis of non-patterned samples using ellipsometry revealed a non-uniformity in etch rate across the samples, regardless of carrier backpressure. The non-uniformity was mitigated when rotating the sample in the sample holder halfway through the CMP process, though this increased the rate of other defects. Patterned samples were found to suffer from dishing and uneven pattern etching. The most optimal configuration was positively patterned samples with a Cr layer under the oxide to enhance etching selectivity. Post CMP, a minimum pattern depth of about 20~nm was achieved with a global variation of about 10~nm due to non-uniformity, which is mostly acceptable for vertical high-power applications. Solvent cleaning and sonication proved insufficient in removing the particulates in slurry residue, highlighting the need for mechanical means of sample cleaning. Post-CMP surface roughness was found to be slightly higher in SiO$_2$ compared to Al$_2$O$_3$, and in general 12 to 35 percent higher than pre-CMP surfaces.}},
  author       = {{Böhm, Paul}},
  language     = {{eng}},
  note         = {{Student Paper}},
  title        = {{Optimizing FinFET Geometry using a Chemical Mechanical Polishing Process}},
  year         = {{2025}},
}