Exploration of a Dynamic Approximate Multiplier for Mixed-Precision Inference
(2026) EITM01 20252Department of Electrical and Information Technology
- Abstract
- The increasing demand for efficient neural network (NN) inference on edge devices has driven the need for hardware-level optimizations that balance computational accuracy with energy and area efficiency. This thesis explores the design and implementation of a dynamic approximate multiplier capable of mixed-precision inference, focusing on floating-point (FP) formats. Using a logarithmic-approximation approach, we implement three precision modes—High Precision Correction (HPC), Low Precision Correction (LPC), and No Correction (NC)—and evaluate their performance on Artix-7 FPGA hardware.
Our results indicate that at 8-bit widths, the numerical error difference between full precision and approximate modes gives a manageable drop off in NN... (More) - The increasing demand for efficient neural network (NN) inference on edge devices has driven the need for hardware-level optimizations that balance computational accuracy with energy and area efficiency. This thesis explores the design and implementation of a dynamic approximate multiplier capable of mixed-precision inference, focusing on floating-point (FP) formats. Using a logarithmic-approximation approach, we implement three precision modes—High Precision Correction (HPC), Low Precision Correction (LPC), and No Correction (NC)—and evaluate their performance on Artix-7 FPGA hardware.
Our results indicate that at 8-bit widths, the numerical error difference between full precision and approximate modes gives a manageable drop off in NN image classification accuracy. Hardware synthesis shows that 8-bit NC and LPC multipliers provide significant advantages in area (number of LUTs) and latency compared to commonly used 8-bit fixed-point multipliers. Furthermore, we demonstrate that a mixed-precision strategy, guided by layer-wise sensitivity, allows for maximizing hardware efficiency while maintaining nearly baseline accuracy. We conclude that approximate 8-bit floating-point multipliers are in some cases a viable alternative to fixed-point arithmetic. (Less) - Popular Abstract
- Artificial Intelligence is everywhere, but the "brains" (Neural Networks) behind it are power-hungry. To make AI run faster and with better battery life on your phone or small devices, a bit of mathematical perfection can be sacrificed. This is called Approximate Computing.
This thesis takes a look at how one of the most common tasks in AI computing can be simplified: multiplication. Normally, computers try to be 100\% accurate. However, AI is surprisingly resilient; it can still "recognize" a cat even if the internal math is somewhat off. In this work, a multiplier is designed that can switch between different levels of "accuracy" on the fly.
By using "smaller" numbers in a physical sense and adjustable approximate math, a design is... (More) - Artificial Intelligence is everywhere, but the "brains" (Neural Networks) behind it are power-hungry. To make AI run faster and with better battery life on your phone or small devices, a bit of mathematical perfection can be sacrificed. This is called Approximate Computing.
This thesis takes a look at how one of the most common tasks in AI computing can be simplified: multiplication. Normally, computers try to be 100\% accurate. However, AI is surprisingly resilient; it can still "recognize" a cat even if the internal math is somewhat off. In this work, a multiplier is designed that can switch between different levels of "accuracy" on the fly.
By using "smaller" numbers in a physical sense and adjustable approximate math, a design is implemented that is cheaper and less power-hungry than other alternatives. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/student-papers/record/9224789
- author
- Weidemann, Eivind Aksel LU
- supervisor
- organization
- course
- EITM01 20252
- year
- 2026
- type
- H2 - Master's Degree (Two Years)
- subject
- keywords
- approximate computing, mixed-precision inference, floating-point multiplier, quantization, neural network inference, logarithmic approximation
- report number
- LU/LTH-EIT 2026-1111
- language
- English
- id
- 9224789
- date added to LUP
- 2026-03-26 10:28:52
- date last changed
- 2026-03-26 10:28:52
@misc{9224789,
abstract = {{The increasing demand for efficient neural network (NN) inference on edge devices has driven the need for hardware-level optimizations that balance computational accuracy with energy and area efficiency. This thesis explores the design and implementation of a dynamic approximate multiplier capable of mixed-precision inference, focusing on floating-point (FP) formats. Using a logarithmic-approximation approach, we implement three precision modes—High Precision Correction (HPC), Low Precision Correction (LPC), and No Correction (NC)—and evaluate their performance on Artix-7 FPGA hardware.
Our results indicate that at 8-bit widths, the numerical error difference between full precision and approximate modes gives a manageable drop off in NN image classification accuracy. Hardware synthesis shows that 8-bit NC and LPC multipliers provide significant advantages in area (number of LUTs) and latency compared to commonly used 8-bit fixed-point multipliers. Furthermore, we demonstrate that a mixed-precision strategy, guided by layer-wise sensitivity, allows for maximizing hardware efficiency while maintaining nearly baseline accuracy. We conclude that approximate 8-bit floating-point multipliers are in some cases a viable alternative to fixed-point arithmetic.}},
author = {{Weidemann, Eivind Aksel}},
language = {{eng}},
note = {{Student Paper}},
title = {{Exploration of a Dynamic Approximate Multiplier for Mixed-Precision Inference}},
year = {{2026}},
}