A Reconfigurable Pipelined ADC in 0.18 um CMOS
(2005) Symposium on VLSI Circuits p.326-329- Abstract
- A reconfigurable pipelined A/D converter has been implemented in a 0.18 mu m RF-CMOS process. The ADC has eight configurations with a top performance of 10 bits resolution at 80 MSPS consuming 94mW. The reconfigurability is achieved by combining the cyclic and pipelined ADC architectures giving it a low level of complexity. In the conventional pipeline mode, the measured SFDR is 69 dBFS and the SNDR is 56.5 dBc for a 1.54 MHz single sinusoid tone input.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/1037969
- author
- Andersson, Martin LU ; Norling, Karl ; Dreyfert, Andreas and Yuan, Jiren LU
- organization
- publishing date
- 2005
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- 2005 Symposium on VLSI Circuits, Digest of Technical Papers
- pages
- 326 - 329
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- Symposium on VLSI Circuits
- conference location
- Kyoto, Japan
- conference dates
- 2005-06-16 - 2005-06-18
- external identifiers
-
- wos:000234973500080
- scopus:33745159381
- ISBN
- 4-900784-01-X
- DOI
- 10.1109/VLSIC.2005.1469397
- language
- English
- LU publication?
- yes
- id
- 92f1504d-39ee-4e99-916f-62f3595f5df0 (old id 1037969)
- date added to LUP
- 2016-04-04 11:46:40
- date last changed
- 2022-04-24 01:12:51
@inproceedings{92f1504d-39ee-4e99-916f-62f3595f5df0, abstract = {{A reconfigurable pipelined A/D converter has been implemented in a 0.18 mu m RF-CMOS process. The ADC has eight configurations with a top performance of 10 bits resolution at 80 MSPS consuming 94mW. The reconfigurability is achieved by combining the cyclic and pipelined ADC architectures giving it a low level of complexity. In the conventional pipeline mode, the measured SFDR is 69 dBFS and the SNDR is 56.5 dBc for a 1.54 MHz single sinusoid tone input.}}, author = {{Andersson, Martin and Norling, Karl and Dreyfert, Andreas and Yuan, Jiren}}, booktitle = {{2005 Symposium on VLSI Circuits, Digest of Technical Papers}}, isbn = {{4-900784-01-X}}, language = {{eng}}, pages = {{326--329}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{A Reconfigurable Pipelined ADC in 0.18 um CMOS}}, url = {{http://dx.doi.org/10.1109/VLSIC.2005.1469397}}, doi = {{10.1109/VLSIC.2005.1469397}}, year = {{2005}}, }