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A Reconfigurable Pipelined ADC in 0.18 um CMOS

Andersson, Martin LU ; Norling, Karl; Dreyfert, Andreas and Yuan, Jiren LU (2005) Symposium on VLSI Circuits In 2005 Symposium on VLSI Circuits, Digest of Technical Papers p.326-329
Abstract
A reconfigurable pipelined A/D converter has been implemented in a 0.18 mu m RF-CMOS process. The ADC has eight configurations with a top performance of 10 bits resolution at 80 MSPS consuming 94mW. The reconfigurability is achieved by combining the cyclic and pipelined ADC architectures giving it a low level of complexity. In the conventional pipeline mode, the measured SFDR is 69 dBFS and the SNDR is 56.5 dBc for a 1.54 MHz single sinusoid tone input.
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
2005 Symposium on VLSI Circuits, Digest of Technical Papers
pages
326 - 329
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
Symposium on VLSI Circuits
external identifiers
  • WOS:000234973500080
  • Scopus:33745159381
ISBN
4-900784-01-X
DOI
10.1109/VLSIC.2005.1469397
language
English
LU publication?
yes
id
92f1504d-39ee-4e99-916f-62f3595f5df0 (old id 1037969)
date added to LUP
2008-02-26 12:57:47
date last changed
2016-10-13 04:47:47
@misc{92f1504d-39ee-4e99-916f-62f3595f5df0,
  abstract     = {A reconfigurable pipelined A/D converter has been implemented in a 0.18 mu m RF-CMOS process. The ADC has eight configurations with a top performance of 10 bits resolution at 80 MSPS consuming 94mW. The reconfigurability is achieved by combining the cyclic and pipelined ADC architectures giving it a low level of complexity. In the conventional pipeline mode, the measured SFDR is 69 dBFS and the SNDR is 56.5 dBc for a 1.54 MHz single sinusoid tone input.},
  author       = {Andersson, Martin and Norling, Karl and Dreyfert, Andreas and Yuan, Jiren},
  isbn         = {4-900784-01-X},
  language     = {eng},
  pages        = {326--329},
  publisher    = {ARRAY(0x8a2ce90)},
  series       = {2005 Symposium on VLSI Circuits, Digest of Technical Papers},
  title        = {A Reconfigurable Pipelined ADC in 0.18 um CMOS},
  url          = {http://dx.doi.org/10.1109/VLSIC.2005.1469397},
  year         = {2005},
}