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A 3.3V low-jitter frequency synthesizer applied to fast Ethernet transceiver

Lu, Ping LU ; Wang, Yan; Li, Lian and Ren, Juyan (2005) The 6th International Conference on ASIC, ASICON 2005 In [Host publication title missing] p.431-434
Abstract
A frequency synthesizer applied to 10/100 Base-T Ethernet transceiver is described. It can work in 10Mbps or 100Mbps mode adaptively and convert from one mode to another freely. The circuit can meet both requirements of transmitter on rising/falling time and receiver on CDR so that the additional power and area are saved. Under some testing circumstance, G of voltage control oscillator jittercycle-cycle is only 22ps with G of reference clock jittercycle-cycle 25ps (Herzel and Razavi, 1997). The testing result proves that the frequency synthesizer has good processing stability and rejection to noises. It works well for transmitter and receiver. The circuit is designed with SMIC 0.35μm standard CMOS technology and the power supply is 3.3V.
Please use this url to cite or link to this publication:
author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
[Host publication title missing]
pages
431 - 434
conference name
The 6th International Conference on ASIC, ASICON 2005
ISBN
0-7803-9210-8
DOI
10.1109/ICASIC.2005.1611345
language
English
LU publication?
no
id
1b2344c6-fdf9-41fd-a9c6-7d478a32281f (old id 1667555)
date added to LUP
2010-09-07 12:44:11
date last changed
2016-06-29 09:07:40
@misc{1b2344c6-fdf9-41fd-a9c6-7d478a32281f,
  abstract     = {A frequency synthesizer applied to 10/100 Base-T Ethernet transceiver is described. It can work in 10Mbps or 100Mbps mode adaptively and convert from one mode to another freely. The circuit can meet both requirements of transmitter on rising/falling time and receiver on CDR so that the additional power and area are saved. Under some testing circumstance, G of voltage control oscillator jittercycle-cycle is only 22ps with G of reference clock jittercycle-cycle 25ps (Herzel and Razavi, 1997). The testing result proves that the frequency synthesizer has good processing stability and rejection to noises. It works well for transmitter and receiver. The circuit is designed with SMIC 0.35μm standard CMOS technology and the power supply is 3.3V.},
  author       = {Lu, Ping and Wang, Yan and Li, Lian and Ren, Juyan},
  isbn         = {0-7803-9210-8},
  language     = {eng},
  pages        = {431--434},
  series       = {[Host publication title missing]},
  title        = {A 3.3V low-jitter frequency synthesizer applied to fast Ethernet transceiver},
  url          = {http://dx.doi.org/10.1109/ICASIC.2005.1611345},
  year         = {2005},
}