Advanced

A low-jitter and low-power frequency synthesizer applied to 1000 Base-T Ethernet

Lu, Ping LU ; Wang, Yan; Li, Liang and Ren, Junyan (2006) In Journal of Semiconductors 27(1). p.137-142
Abstract
This paper adopts a high-speed TSPC frequency and phase detector,a typical charge pump,and cross-coupled differential delay cells to realized a good frequency synthesizer applied to 1000Base-T Ethernet transceiver as well as 10/100Mbps modes.This frequency synthesizer can not only meet the requirements of the transmitter for very precise rising (falling) edge time control but also offer much finer time-interval clocks than VCO natural multi-phase outputs,thus greatly saving area and power.The data show that the σ of the voltage control oscillator jitter_ cycle-cycle is only 11ps while that of the reference clock jitter_ cycle-cycle is 16ps.This indicates that the frequency synthesizer works well for transmitters and receivers.The circuit... (More)
This paper adopts a high-speed TSPC frequency and phase detector,a typical charge pump,and cross-coupled differential delay cells to realized a good frequency synthesizer applied to 1000Base-T Ethernet transceiver as well as 10/100Mbps modes.This frequency synthesizer can not only meet the requirements of the transmitter for very precise rising (falling) edge time control but also offer much finer time-interval clocks than VCO natural multi-phase outputs,thus greatly saving area and power.The data show that the σ of the voltage control oscillator jitter_ cycle-cycle is only 11ps while that of the reference clock jitter_ cycle-cycle is 16ps.This indicates that the frequency synthesizer works well for transmitters and receivers.The circuit is designed with SMIC 0.18μm standard CMOS technology,the power supply is 1.8V,and the power is lower than 4mW. (Less)
Please use this url to cite or link to this publication:
author
publishing date
type
Contribution to journal
publication status
published
subject
keywords
Ethernet frequency synthesizer clock jitter
in
Journal of Semiconductors
volume
27
issue
1
pages
137 - 142
publisher
IOS Press
external identifiers
  • Scopus:33646163894
ISSN
1674-4926
language
Chinese
LU publication?
no
id
d88ccbc6-7cf1-4905-871a-33de49adfa1c (old id 1667591)
alternative location
http://en.cnki.com.cn/Article_en/CJFDTOTAL-BDTX200601028.htm
date added to LUP
2010-09-07 11:26:03
date last changed
2016-10-13 04:25:58
@misc{d88ccbc6-7cf1-4905-871a-33de49adfa1c,
  abstract     = {This paper adopts a high-speed TSPC frequency and phase detector,a typical charge pump,and cross-coupled differential delay cells to realized a good frequency synthesizer applied to 1000Base-T Ethernet transceiver as well as 10/100Mbps modes.This frequency synthesizer can not only meet the requirements of the transmitter for very precise rising (falling) edge time control but also offer much finer time-interval clocks than VCO natural multi-phase outputs,thus greatly saving area and power.The data show that the σ of the voltage control oscillator jitter_ cycle-cycle is only 11ps while that of the reference clock jitter_ cycle-cycle is 16ps.This indicates that the frequency synthesizer works well for transmitters and receivers.The circuit is designed with SMIC 0.18μm standard CMOS technology,the power supply is 1.8V,and the power is lower than 4mW.},
  author       = {Lu, Ping and Wang, Yan and Li, Liang and Ren, Junyan},
  issn         = {1674-4926},
  keyword      = {Ethernet frequency synthesizer clock jitter},
  language     = {chi},
  number       = {1},
  pages        = {137--142},
  publisher    = {ARRAY(0x833c3b8)},
  series       = {Journal of Semiconductors},
  title        = {A low-jitter and low-power frequency synthesizer applied to 1000 Base-T Ethernet},
  volume       = {27},
  year         = {2006},
}