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Bit-serial realization of maximum and minimum filters

Yuan, Jiren LU and Chen, Keping (1988) In Electronics Letters 24(8). p.485-486
Abstract
Efficient bit-serial realisations for maximum and minimum filters are presented. The proposed circuits are simple and suitable for VLSI implementation. The filters not only give the maximum or minimum values, but also indicate which input is the maximum or minimum in an input vector. A true single phase clock has been used to achieve high speed
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author
publishing date
type
Contribution to journal
publication status
published
subject
in
Electronics Letters
volume
24
issue
8
pages
485 - 486
publisher
IEE
ISSN
1350-911X
language
English
LU publication?
no
id
208459f2-0200-47fe-80ae-7c69178bf6b3 (old id 1758996)
alternative location
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8250
date added to LUP
2011-01-04 18:21:45
date last changed
2016-06-29 09:00:20
@misc{208459f2-0200-47fe-80ae-7c69178bf6b3,
  abstract     = {Efficient bit-serial realisations for maximum and minimum filters are presented. The proposed circuits are simple and suitable for VLSI implementation. The filters not only give the maximum or minimum values, but also indicate which input is the maximum or minimum in an input vector. A true single phase clock has been used to achieve high speed},
  author       = {Yuan, Jiren and Chen, Keping},
  issn         = {1350-911X},
  language     = {eng},
  number       = {8},
  pages        = {485--486},
  publisher    = {ARRAY(0xa05f220)},
  series       = {Electronics Letters},
  title        = {Bit-serial realization of maximum and minimum filters},
  volume       = {24},
  year         = {1988},
}