CMOS circuit speed optimization based on switch level simulation
(1988) IEEE International Symposium on Circuits and Systems, 1988 3. p.2109-2112- Abstract
- The authors present a tool for transistor sizing for the purpose of speed optimization. The tool, called SLOP (switch-level optimization), is based on a switch-level simulation program for CMOS circuits. Consequently, the results are always verified by simulation. It gives the delay-area curve and the final sizes of each transistor according to the maximum width limitation specified by the user. Experimental results are presented. The typical improvement in circuit speed is 60%-90% with an area increase of 80%-110%.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/1761716
- author
- Yuan, Jiren LU and Svensson, Christer
- publishing date
- 1988
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- [Host publication title missing]
- volume
- 3
- pages
- 2109 - 2112
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- IEEE International Symposium on Circuits and Systems, 1988
- conference location
- Espoo, Finland
- conference dates
- 1988-06-07 - 1988-06-09
- external identifiers
-
- scopus:0024124575
- DOI
- 10.1109/ISCAS.1988.15358
- language
- English
- LU publication?
- no
- id
- d70106ee-5d0a-4987-90f9-f683e8011bd0 (old id 1761716)
- date added to LUP
- 2016-04-04 11:22:28
- date last changed
- 2021-09-12 04:05:47
@inproceedings{d70106ee-5d0a-4987-90f9-f683e8011bd0, abstract = {{The authors present a tool for transistor sizing for the purpose of speed optimization. The tool, called SLOP (switch-level optimization), is based on a switch-level simulation program for CMOS circuits. Consequently, the results are always verified by simulation. It gives the delay-area curve and the final sizes of each transistor according to the maximum width limitation specified by the user. Experimental results are presented. The typical improvement in circuit speed is 60%-90% with an area increase of 80%-110%.}}, author = {{Yuan, Jiren and Svensson, Christer}}, booktitle = {{[Host publication title missing]}}, language = {{eng}}, pages = {{2109--2112}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{CMOS circuit speed optimization based on switch level simulation}}, url = {{http://dx.doi.org/10.1109/ISCAS.1988.15358}}, doi = {{10.1109/ISCAS.1988.15358}}, volume = {{3}}, year = {{1988}}, }