Advanced

CMOS circuit speed optimization based on switch level simulation

Yuan, Jiren LU and Svensson, Christer (1988) IEEE International Symposium on Circuits and Systems, 1988 In [Host publication title missing] 3. p.2109-2112
Abstract
The authors present a tool for transistor sizing for the purpose of speed optimization. The tool, called SLOP (switch-level optimization), is based on a switch-level simulation program for CMOS circuits. Consequently, the results are always verified by simulation. It gives the delay-area curve and the final sizes of each transistor according to the maximum width limitation specified by the user. Experimental results are presented. The typical improvement in circuit speed is 60%-90% with an area increase of 80%-110%.
Please use this url to cite or link to this publication:
author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
[Host publication title missing]
volume
3
pages
2109 - 2112
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE International Symposium on Circuits and Systems, 1988
external identifiers
  • Scopus:0024124575
DOI
10.1109/ISCAS.1988.15358
language
English
LU publication?
no
id
d70106ee-5d0a-4987-90f9-f683e8011bd0 (old id 1761716)
date added to LUP
2011-01-11 15:40:47
date last changed
2016-10-13 04:45:23
@misc{d70106ee-5d0a-4987-90f9-f683e8011bd0,
  abstract     = {The authors present a tool for transistor sizing for the purpose of speed optimization. The tool, called SLOP (switch-level optimization), is based on a switch-level simulation program for CMOS circuits. Consequently, the results are always verified by simulation. It gives the delay-area curve and the final sizes of each transistor according to the maximum width limitation specified by the user. Experimental results are presented. The typical improvement in circuit speed is 60%-90% with an area increase of 80%-110%.},
  author       = {Yuan, Jiren and Svensson, Christer},
  language     = {eng},
  pages        = {2109--2112},
  publisher    = {ARRAY(0x9d6ef78)},
  series       = {[Host publication title missing]},
  title        = {CMOS circuit speed optimization based on switch level simulation},
  url          = {http://dx.doi.org/10.1109/ISCAS.1988.15358},
  volume       = {3},
  year         = {1988},
}