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Graph Theoretic Approach for Scan Cell Reordering to Minimize Peak Shift Power

Tudu, Jaynarayan T.; Larsson, Erik LU ; Singh, Virendra and Fujiwara, Hideo (2010) Great Lakes Symposium on VLSI (GLSVLSI'10) In GLSVLSI '10 Proceedings of the 20th symposium on Great lakes symposium on VLSI p.73-78
Abstract
Scan circuit testing generally causes excessive switching activity compared to normal circuit operation. This excessive switching activity causes high peak and average power consumption. Higher peak power causes, supply voltage droop and excessive heat dissipation. This paper proposes a scan cell reordering methodology to minimize the peak power consumption during scan shift operation. The proposed methodology first formulate the problem as graph theoretic problem then solve it by a linear time heuristic. The experimental results show that the methodology is able to reduce up to 48% of peak power in compared to the solution provided by industrial tool.
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author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
GLSVLSI '10 Proceedings of the 20th symposium on Great lakes symposium on VLSI
pages
73 - 78
conference name
Great Lakes Symposium on VLSI (GLSVLSI'10)
external identifiers
  • Scopus:77954517874
ISBN
978-1-4503-0012-4
DOI
10.1145/1785481.1785499
language
English
LU publication?
no
id
c2ae2e36-3636-4133-8ea5-c1a127aee2b8 (old id 2340833)
date added to LUP
2012-02-10 13:59:53
date last changed
2016-10-13 05:06:08
@misc{c2ae2e36-3636-4133-8ea5-c1a127aee2b8,
  abstract     = {Scan circuit testing generally causes excessive switching activity compared to normal circuit operation. This excessive switching activity causes high peak and average power consumption. Higher peak power causes, supply voltage droop and excessive heat dissipation. This paper proposes a scan cell reordering methodology to minimize the peak power consumption during scan shift operation. The proposed methodology first formulate the problem as graph theoretic problem then solve it by a linear time heuristic. The experimental results show that the methodology is able to reduce up to 48% of peak power in compared to the solution provided by industrial tool.},
  author       = {Tudu, Jaynarayan T. and Larsson, Erik and Singh, Virendra and Fujiwara, Hideo},
  isbn         = {978-1-4503-0012-4},
  language     = {eng},
  pages        = {73--78},
  series       = {GLSVLSI '10 Proceedings of the 20th symposium on Great lakes symposium on VLSI},
  title        = {Graph Theoretic Approach for Scan Cell Reordering to Minimize Peak Shift Power},
  url          = {http://dx.doi.org/10.1145/1785481.1785499},
  year         = {2010},
}