A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
(2007) IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2007 p.61-61- Abstract
- The increasingcost for System-on-Chip (SOC) testing is mainly due to the hugetest data volumes that lead to long test application time andrequire large automatic test equipment (ATE) memory. Testcompression and test sharing have been proposed to reduce the testdata volume, while test infrastructure and concurrent testscheduling have been developed to reduce the test application time.In this work we propose an integrated test scheduling and testinfrastructure design approach that utilizes both test compressionand test sharing as basic mechanisms to reduce test data volumes.In particular, we have developed a heuristic to minimize the testapplication time, considering different alternatives of testcompression and sharing, without violating a... (More)
- The increasingcost for System-on-Chip (SOC) testing is mainly due to the hugetest data volumes that lead to long test application time andrequire large automatic test equipment (ATE) memory. Testcompression and test sharing have been proposed to reduce the testdata volume, while test infrastructure and concurrent testscheduling have been developed to reduce the test application time.In this work we propose an integrated test scheduling and testinfrastructure design approach that utilizes both test compressionand test sharing as basic mechanisms to reduce test data volumes.In particular, we have developed a heuristic to minimize the testapplication time, considering different alternatives of testcompression and sharing, without violating a given ATE memoryconstraint. The results from the proposed Tabu Search basedheuristic have been validated using benchmark designs and arecompared with optimal solutions. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2341003
- author
- Larsson, Anders ; Larsson, Erik LU ; Eles, Petru Ion and Peng, Zebo
- organization
- publishing date
- 2007
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- testing, system-on-chip, memory reduction, test scheduling, test data compression, test sharing, tabu search
- host publication
- [Host publication title missing]
- pages
- 61 - 61
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2007
- conference location
- Krakow, Poland
- conference dates
- 2007-04-11 - 2007-04-13
- external identifiers
-
- scopus:46449124284
- ISBN
- 1-4244-1162-9
- DOI
- 10.1109/DDECS.2007.4295255
- language
- English
- LU publication?
- no
- id
- bf150b02-a621-456c-a8c9-db51e5d97edb (old id 2341003)
- date added to LUP
- 2016-04-04 10:49:12
- date last changed
- 2022-04-08 06:15:19
@inproceedings{bf150b02-a621-456c-a8c9-db51e5d97edb, abstract = {{The increasingcost for System-on-Chip (SOC) testing is mainly due to the hugetest data volumes that lead to long test application time andrequire large automatic test equipment (ATE) memory. Testcompression and test sharing have been proposed to reduce the testdata volume, while test infrastructure and concurrent testscheduling have been developed to reduce the test application time.In this work we propose an integrated test scheduling and testinfrastructure design approach that utilizes both test compressionand test sharing as basic mechanisms to reduce test data volumes.In particular, we have developed a heuristic to minimize the testapplication time, considering different alternatives of testcompression and sharing, without violating a given ATE memoryconstraint. The results from the proposed Tabu Search basedheuristic have been validated using benchmark designs and arecompared with optimal solutions.}}, author = {{Larsson, Anders and Larsson, Erik and Eles, Petru Ion and Peng, Zebo}}, booktitle = {{[Host publication title missing]}}, isbn = {{1-4244-1162-9}}, keywords = {{testing; system-on-chip; memory reduction; test scheduling; test data compression; test sharing; tabu search}}, language = {{eng}}, pages = {{61--61}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing}}, url = {{http://dx.doi.org/10.1109/DDECS.2007.4295255}}, doi = {{10.1109/DDECS.2007.4295255}}, year = {{2007}}, }