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Optimized Integration of Test Compression and Sharing for SOC Testing

Larsson, Anders; Larsson, Erik LU ; Eles, Petru Ion and Peng, Zebo (2007) Design, Automation, and Test in Europe Conference DATE07 In [Host publication title missing] p.207-207
Abstract
The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requirements. TAT and ATE memory requirement can be reduced by test architecture design, test scheduling, sharing the same tests among several cores, and test data compression. We propose, in contrast to previous work that addresses one or few of the problems, an integrated framework with heuristics for sharing and compression and a Constraint Logic Programming technique for architecture design and test scheduling that minimizes the TAT without violating a given ATE memory constraint. The significance of our approach is demonstrated by experiments with ITC-02 benchmark... (More)
The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requirements. TAT and ATE memory requirement can be reduced by test architecture design, test scheduling, sharing the same tests among several cores, and test data compression. We propose, in contrast to previous work that addresses one or few of the problems, an integrated framework with heuristics for sharing and compression and a Constraint Logic Programming technique for architecture design and test scheduling that minimizes the TAT without violating a given ATE memory constraint. The significance of our approach is demonstrated by experiments with ITC-02 benchmark designs. (Less)
Please use this url to cite or link to this publication:
author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
testing, system-on-chip, SOC, test scheduling, memory requirements, test data compression, constraint logic programming
in
[Host publication title missing]
pages
207 - 207
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
Design, Automation, and Test in Europe Conference DATE07
external identifiers
  • Scopus:34548314162
ISBN
978-3-9810801-2-4
DOI
10.1109/DATE.2007.364592
language
English
LU publication?
no
id
ed253fa2-1e38-4323-b0ab-7ab9e5e2a07c (old id 2341020)
date added to LUP
2012-02-10 13:39:45
date last changed
2016-10-13 04:45:07
@misc{ed253fa2-1e38-4323-b0ab-7ab9e5e2a07c,
  abstract     = {The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requirements. TAT and ATE memory requirement can be reduced by test architecture design, test scheduling, sharing the same tests among several cores, and test data compression. We propose, in contrast to previous work that addresses one or few of the problems, an integrated framework with heuristics for sharing and compression and a Constraint Logic Programming technique for architecture design and test scheduling that minimizes the TAT without violating a given ATE memory constraint. The significance of our approach is demonstrated by experiments with ITC-02 benchmark designs.},
  author       = {Larsson, Anders and Larsson, Erik and Eles, Petru Ion and Peng, Zebo},
  isbn         = {978-3-9810801-2-4},
  keyword      = {testing,system-on-chip,SOC,test scheduling,memory requirements,test data compression,constraint logic programming},
  language     = {eng},
  pages        = {207--207},
  publisher    = {ARRAY(0x933f840)},
  series       = {[Host publication title missing]},
  title        = {Optimized Integration of Test Compression and Sharing for SOC Testing},
  url          = {http://dx.doi.org/10.1109/DATE.2007.364592},
  year         = {2007},
}