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Combined Test Data Compression and Abort-on-Fail Test

Larsson, Erik LU (2006) NORCHIP Conference, 2006 In [Host publication title missing] p.137-140
Abstract
The increasing test data volume needed for the testing of System-on-Chips (SOCs) leads to high Automatic Test Equipment (ATE) memory requirement and long test application times. Scheduling techniques where testing can be terminated as soon as a fault appears (abort-on-fail) as well as efficient compression schemes to reduce the ATE memory requirement have been proposed separately. Previous test data compression architectures often make use of Multiple Input Signature Response Analyzers (MISRs) for response compression. Therefore, abort-on-fail testing and diagnostic capabilities are limited. In this paper, we propose an SOC test architecture that (1) allows test data compression, (2) where clock cycle based as well as patternbased... (More)
The increasing test data volume needed for the testing of System-on-Chips (SOCs) leads to high Automatic Test Equipment (ATE) memory requirement and long test application times. Scheduling techniques where testing can be terminated as soon as a fault appears (abort-on-fail) as well as efficient compression schemes to reduce the ATE memory requirement have been proposed separately. Previous test data compression architectures often make use of Multiple Input Signature Response Analyzers (MISRs) for response compression. Therefore, abort-on-fail testing and diagnostic capabilities are limited. In this paper, we propose an SOC test architecture that (1) allows test data compression, (2) where clock cycle based as well as patternbased abort-on-fail testing are allowed and (3) diagnostic capabilities are not reduced. We have performed experiments on ISCAS designs. (Less)
Please use this url to cite or link to this publication:
author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
testing, test data, compression, abort-on-fail
in
[Host publication title missing]
pages
137 - 140
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
NORCHIP Conference, 2006
external identifiers
  • Scopus:34547254766
ISBN
1-4244-0772-9
DOI
10.1109/NORCHP.2006.329262
language
English
LU publication?
no
id
fd6286a9-d4f3-4b0c-a083-1bb4d28f879f (old id 2341031)
date added to LUP
2012-02-10 13:38:27
date last changed
2016-10-13 04:50:52
@misc{fd6286a9-d4f3-4b0c-a083-1bb4d28f879f,
  abstract     = {The increasing test data volume needed for the testing of System-on-Chips (SOCs) leads to high Automatic Test Equipment (ATE) memory requirement and long test application times. Scheduling techniques where testing can be terminated as soon as a fault appears (abort-on-fail) as well as efficient compression schemes to reduce the ATE memory requirement have been proposed separately. Previous test data compression architectures often make use of Multiple Input Signature Response Analyzers (MISRs) for response compression. Therefore, abort-on-fail testing and diagnostic capabilities are limited. In this paper, we propose an SOC test architecture that (1) allows test data compression, (2) where clock cycle based as well as patternbased abort-on-fail testing are allowed and (3) diagnostic capabilities are not reduced. We have performed experiments on ISCAS designs.},
  author       = {Larsson, Erik},
  isbn         = {1-4244-0772-9},
  keyword      = {testing,test data,compression,abort-on-fail},
  language     = {eng},
  pages        = {137--140},
  publisher    = {ARRAY(0xa9f5e30)},
  series       = {[Host publication title missing]},
  title        = {Combined Test Data Compression and Abort-on-Fail Test},
  url          = {http://dx.doi.org/10.1109/NORCHP.2006.329262},
  year         = {2006},
}