A High-Speed QR Decomposition Processor for Carrier-Aggregated LTE-A Downlink Systems
(2013) European Conference on Circuit Theory and Design (ECCTD 2013)- Abstract
- This paper presents a high-speed QR decomposition (QRD) processor targeting the carrier-aggregated 4 × 4 Long Term Evolution-Advanced (LTE-A) receiver. The processor provides robustness in spatially correlated channels with reduced complexity by using modifications to the Householder transform, such as decomposing-target redefinition and matrix real-valued decomposition. In terms of hardware design, we extensively explore flexibilities in systolic architectures using a high-level synthesis tool to achieve area-power efficiency. In a 65 nm CMOS technology, the processor occupies a core area of 0.77mm2 and produces 72MQRD per second, the highest reported throughput. The power consumed in the proposed processor is 219mW.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/4023949
- author
- Gangarajaiah, Rakesh LU ; Liu, Liang LU ; Stala, Michal LU ; Nilsson, Peter LU and Edfors, Ove LU
- organization
- publishing date
- 2013
- type
- Contribution to conference
- publication status
- published
- subject
- pages
- 4 pages
- conference name
- European Conference on Circuit Theory and Design (ECCTD 2013)
- conference location
- Dresden, Germany
- conference dates
- 2013-09-08 - 2013-09-12
- external identifiers
-
- scopus:84892629955
- language
- English
- LU publication?
- yes
- id
- 8e361bcb-08c1-4180-baf5-8269eb013e34 (old id 4023949)
- date added to LUP
- 2016-04-04 14:11:36
- date last changed
- 2024-01-13 11:38:17
@misc{8e361bcb-08c1-4180-baf5-8269eb013e34, abstract = {{This paper presents a high-speed QR decomposition (QRD) processor targeting the carrier-aggregated 4 × 4 Long Term Evolution-Advanced (LTE-A) receiver. The processor provides robustness in spatially correlated channels with reduced complexity by using modifications to the Householder transform, such as decomposing-target redefinition and matrix real-valued decomposition. In terms of hardware design, we extensively explore flexibilities in systolic architectures using a high-level synthesis tool to achieve area-power efficiency. In a 65 nm CMOS technology, the processor occupies a core area of 0.77mm2 and produces 72MQRD per second, the highest reported throughput. The power consumed in the proposed processor is 219mW.}}, author = {{Gangarajaiah, Rakesh and Liu, Liang and Stala, Michal and Nilsson, Peter and Edfors, Ove}}, language = {{eng}}, title = {{A High-Speed QR Decomposition Processor for Carrier-Aggregated LTE-A Downlink Systems}}, url = {{https://lup.lub.lu.se/search/files/6302453/8851509.pdf}}, year = {{2013}}, }