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Scenario-Based Network Design for P1687

Ghani Zadegan, Farrokh LU ; Carlsson, Gunnar and Larsson, Erik LU (2013) Swedish System-On-Chip Conference (SSoCC), 2013
Abstract
To improve testability of integrated circuits against manufacturing defects, and to better handle the complexity of modern designs during debugging and characterization, it is common to embed testing, debugging, configuration, and monitoring features (called on-chip instruments) within the chip. IEEE P1687 proposes a flexible network for accessing and operating such on-chip instruments from outside the chip, and facilitates reusing instrument access procedures in different usage scenarios throughout the chip's life-cycle-spanning from chip prototyping to in-field test. Efficient access (in terms of time) to on-chip instruments requires careful design of the instrument access network. However, it is shown that a network optimized for one... (More)
To improve testability of integrated circuits against manufacturing defects, and to better handle the complexity of modern designs during debugging and characterization, it is common to embed testing, debugging, configuration, and monitoring features (called on-chip instruments) within the chip. IEEE P1687 proposes a flexible network for accessing and operating such on-chip instruments from outside the chip, and facilitates reusing instrument access procedures in different usage scenarios throughout the chip's life-cycle-spanning from chip prototyping to in-field test. Efficient access (in terms of time) to on-chip instruments requires careful design of the instrument access network. However, it is shown that a network optimized for one usage scenario, is not necessarily efficient in other scenarios. To address the problem of designing a network which is efficient in terms of instrument access time under multiple scenarios, in this work, we compare a number of network design approaches provided by P1687, in terms of instrument access time and hardware overhead. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to conference
publication status
published
subject
keywords
IEEE P1687 (IJTAG), on-chip instruments, access time, test time, ICL, network design
conference name
Swedish System-On-Chip Conference (SSoCC), 2013
language
English
LU publication?
yes
id
017977ef-a80a-4ca0-afcb-9982e756a7ba (old id 4285334)
date added to LUP
2014-02-10 10:37:02
date last changed
2016-07-15 08:48:57
@misc{017977ef-a80a-4ca0-afcb-9982e756a7ba,
  abstract     = {To improve testability of integrated circuits against manufacturing defects, and to better handle the complexity of modern designs during debugging and characterization, it is common to embed testing, debugging, configuration, and monitoring features (called on-chip instruments) within the chip. IEEE P1687 proposes a flexible network for accessing and operating such on-chip instruments from outside the chip, and facilitates reusing instrument access procedures in different usage scenarios throughout the chip's life-cycle-spanning from chip prototyping to in-field test. Efficient access (in terms of time) to on-chip instruments requires careful design of the instrument access network. However, it is shown that a network optimized for one usage scenario, is not necessarily efficient in other scenarios. To address the problem of designing a network which is efficient in terms of instrument access time under multiple scenarios, in this work, we compare a number of network design approaches provided by P1687, in terms of instrument access time and hardware overhead.},
  author       = {Ghani Zadegan, Farrokh and Carlsson, Gunnar and Larsson, Erik},
  keyword      = {IEEE P1687 (IJTAG),on-chip instruments,access time,test time,ICL,network design},
  language     = {eng},
  title        = {Scenario-Based Network Design for P1687},
  year         = {2013},
}