Advanced

Graph Matching Constraints for Synthesis with Complex Components

Fuentes, Ana LU and Kuchcinski, Krzysztof LU (2007) 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools In Proceedings of the Euromicro Symposium on Digital System Design p.288-295
Abstract
In this paper we present a new method for high-level synthesis that enhances design flexibility, specialization and performance primarily conceived for programmable hardware. New programmable hardware devices often provide fast dedicated components that perform complex computations. Arbitrary complex computations can be efficiently extracted from the CDFG using our new graph matching constraint to produce final implementations that better suit the design to the targeted architecture. Our algorithm also reduces possible syntactic variances detecting semantically equivalent structures in the graph. This new graph matching constraint was integrated in our own Constraint Programming solver engine together with other constraints to naturally... (More)
In this paper we present a new method for high-level synthesis that enhances design flexibility, specialization and performance primarily conceived for programmable hardware. New programmable hardware devices often provide fast dedicated components that perform complex computations. Arbitrary complex computations can be efficiently extracted from the CDFG using our new graph matching constraint to produce final implementations that better suit the design to the targeted architecture. Our algorithm also reduces possible syntactic variances detecting semantically equivalent structures in the graph. This new graph matching constraint was integrated in our own Constraint Programming solver engine together with other constraints to naturally model the heterogeneous features present in the synthesis problem. The use of complex functional modules is taken into account in the optimization process during binding and scheduling yielding significantly shorter schedules and gains in terms of area and performance. We demonstrate our technique on a variety of HLS benchmarks and show that efficient design space exploration can be accomplished using this technique. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
Proceedings of the Euromicro Symposium on Digital System Design
pages
8 pages
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
external identifiers
  • WOS:000251463100040
  • Scopus:47749152230
ISBN
978-0-7695-2978-3
DOI
10.1109/DSD.2007.4341482
language
English
LU publication?
yes
id
1bd24245-52fe-4ec9-b4e8-d5f409558548 (old id 622435)
date added to LUP
2007-11-23 13:04:02
date last changed
2016-10-13 04:49:08
@misc{1bd24245-52fe-4ec9-b4e8-d5f409558548,
  abstract     = {In this paper we present a new method for high-level synthesis that enhances design flexibility, specialization and performance primarily conceived for programmable hardware. New programmable hardware devices often provide fast dedicated components that perform complex computations. Arbitrary complex computations can be efficiently extracted from the CDFG using our new graph matching constraint to produce final implementations that better suit the design to the targeted architecture. Our algorithm also reduces possible syntactic variances detecting semantically equivalent structures in the graph. This new graph matching constraint was integrated in our own Constraint Programming solver engine together with other constraints to naturally model the heterogeneous features present in the synthesis problem. The use of complex functional modules is taken into account in the optimization process during binding and scheduling yielding significantly shorter schedules and gains in terms of area and performance. We demonstrate our technique on a variety of HLS benchmarks and show that efficient design space exploration can be accomplished using this technique.},
  author       = {Fuentes, Ana and Kuchcinski, Krzysztof},
  isbn         = {978-0-7695-2978-3},
  language     = {eng},
  pages        = {288--295},
  publisher    = {ARRAY(0xa7e1de8)},
  series       = {Proceedings of the Euromicro Symposium on Digital System Design},
  title        = {Graph Matching Constraints for Synthesis with Complex Components},
  url          = {http://dx.doi.org/10.1109/DSD.2007.4341482},
  year         = {2007},
}