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VHDL vs. Bluespec System Verilog: A case study on a Java embedded architecture

Gruian, Flavius LU and Westmijze, Mark (2008) Symposium on Applied Computing (SAC) In Proceedings of the 23rd Annual Acm Symposium on Applied Computing p.1492-1497
Abstract
This paper compares two hardware design flows, based on the classic VHDL on one side and the relatively new Bluespec System Verilog (BSV) on the other side. The comparison is based on a case study of a Java embedded architecture, comprising a Java native processor and a memory management unit. The processor is a micro-programmed, pipelined, Java-optimized processor (JOP), initially written in VHDL, and its BSV re-designed match BLUEJEP. Its memory management unit implements the bytecodes dealing with memory allocation, along with a mark-compact garbage collector. The two design flows are examined from several points of view, including both quantitative and qualitative measures. Based on this design experience, we conclude that the new... (More)
This paper compares two hardware design flows, based on the classic VHDL on one side and the relatively new Bluespec System Verilog (BSV) on the other side. The comparison is based on a case study of a Java embedded architecture, comprising a Java native processor and a memory management unit. The processor is a micro-programmed, pipelined, Java-optimized processor (JOP), initially written in VHDL, and its BSV re-designed match BLUEJEP. Its memory management unit implements the bytecodes dealing with memory allocation, along with a mark-compact garbage collector. The two design flows are examined from several points of view, including both quantitative and qualitative measures. Based on this design experience, we conclude that the new high-abstraction level languages, such as BSV, offer in comparison to register-transfer (RT) level classic approaches roughly the same trade-offs that C++ offers vs. assembly language in the software world. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Java processor, embedded systems, Bluespec
in
Proceedings of the 23rd Annual Acm Symposium on Applied Computing
pages
1492 - 1497
publisher
ACM
conference name
Symposium on Applied Computing (SAC)
external identifiers
  • WOS:000268392201125
  • Scopus:56749101675
DOI
10.1145/1363686.1364037
language
English
LU publication?
yes
id
77fc25f6-3f7b-4f6f-862a-618713db1ffa (old id 622816)
date added to LUP
2007-12-10 10:26:59
date last changed
2016-10-13 04:40:59
@misc{77fc25f6-3f7b-4f6f-862a-618713db1ffa,
  abstract     = {This paper compares two hardware design flows, based on the classic VHDL on one side and the relatively new Bluespec System Verilog (BSV) on the other side. The comparison is based on a case study of a Java embedded architecture, comprising a Java native processor and a memory management unit. The processor is a micro-programmed, pipelined, Java-optimized processor (JOP), initially written in VHDL, and its BSV re-designed match BLUEJEP. Its memory management unit implements the bytecodes dealing with memory allocation, along with a mark-compact garbage collector. The two design flows are examined from several points of view, including both quantitative and qualitative measures. Based on this design experience, we conclude that the new high-abstraction level languages, such as BSV, offer in comparison to register-transfer (RT) level classic approaches roughly the same trade-offs that C++ offers vs. assembly language in the software world.},
  author       = {Gruian, Flavius and Westmijze, Mark},
  keyword      = {Java processor,embedded systems,Bluespec},
  language     = {eng},
  pages        = {1492--1497},
  publisher    = {ARRAY(0xb5931d0)},
  series       = {Proceedings of the 23rd Annual Acm Symposium on Applied Computing},
  title        = {VHDL vs. Bluespec System Verilog: A case study on a Java embedded architecture},
  url          = {http://dx.doi.org/10.1145/1363686.1364037},
  year         = {2008},
}