Development of a new verification environment for a GPU hardware block using the Universal Verification Methodology
(2020) EITM01 20201Department of Electrical and Information Technology
- Abstract
- The invention of the integrated circuit is a key milestone in the history of electronic circuits. Since its introduction the number of components on a chip have increased rapidly, making them more powerful and able to perform complex operations, but it has also changed the design process. Today different parts of a chip can be developed separately as Intellectual Property (IP) and then put together to form the final system.
Over the last years making sure that the design follows the specification, also known as functional verification, have become a key part of the development life cycle. Finding bugs early is crucial for keeping cost down and achieving time-to-market requirements. This means that as the complexity of the design... (More) - The invention of the integrated circuit is a key milestone in the history of electronic circuits. Since its introduction the number of components on a chip have increased rapidly, making them more powerful and able to perform complex operations, but it has also changed the design process. Today different parts of a chip can be developed separately as Intellectual Property (IP) and then put together to form the final system.
Over the last years making sure that the design follows the specification, also known as functional verification, have become a key part of the development life cycle. Finding bugs early is crucial for keeping cost down and achieving time-to-market requirements. This means that as the complexity of the design continues to increase, the time needed to thoroughly verify it cannot follow the same line of increment. This has pushed engineers to come up with new tools and methodologies to improve the verification process.
The Universal Verification Methodology (UVM) is created by Accellera together with experts from electronic design automation vendors Synopsys, Mentor and Cadence. Its emphasis is on improving the development of verification environments by increasing interoperability and making it easier to reuse verification components.
This project will develop a new verification environment verification environment according to the Universal Verification Methodology to investigate how it can be implemented when separately developed blocks are verified together. A hardware block with sub-components from a Graphics Processing Unit (GPU) will be used and the methodology will be analysed based on how it affects the structure and performance of the verification environment. The dissertation will result in a new implemented verification environment along with guidelines on how to possibly improve block-integrating verification in general and verification of graphics processor specifically. (Less) - Popular Abstract (Swedish)
- Uppfinnandet av den integrerade kretsen banade väg för dagens datorer, mobiltelefoner och all annan elektronik som är en självklar del av vår vardag. En integrerad krets består idag av hundramiljontals halvledarkomponenter som sitter ihop med varandra på ett så kallat chip. Komplexiteten och antalet komponenter på chipen fortsätter att öka vilket har förändrat utvecklingsprocessen. Ett chip som tidigare sågs som ett system utvecklas idag som separata block och monteras sedan ihop till det slutliga systemet. För att företag ska kunna hålla produktionstiden kort och kostnaderna låga har verifikation med åren blivit en allt viktigare del i utvecklingen av integrerade kretsar. Verifikation innebär att en krets kontrolleras så att den uppfyller... (More)
- Uppfinnandet av den integrerade kretsen banade väg för dagens datorer, mobiltelefoner och all annan elektronik som är en självklar del av vår vardag. En integrerad krets består idag av hundramiljontals halvledarkomponenter som sitter ihop med varandra på ett så kallat chip. Komplexiteten och antalet komponenter på chipen fortsätter att öka vilket har förändrat utvecklingsprocessen. Ett chip som tidigare sågs som ett system utvecklas idag som separata block och monteras sedan ihop till det slutliga systemet. För att företag ska kunna hålla produktionstiden kort och kostnaderna låga har verifikation med åren blivit en allt viktigare del i utvecklingen av integrerade kretsar. Verifikation innebär att en krets kontrolleras så att den uppfyller kraven i specifikationen innan den skickas för tillverkning genom att simulera designen. Därigenom kan eventuella fel upptäckas och åtgärdas tidigt i utvecklingsprocessen.
För att verifiera kretsen används en verifieringsmiljö, även kallat testbänk, vars uppgift är att generera insignaler till designen och sedan samla in utsignalerna. Genom att analysera utsignalerna går det att avgöra om kretsen har korrekt beteende eller om fel behöver åtgärdas. I takt med att antalet komponenter ökar och kretsarna blir mer avancerade ökar också svårigheten i att på ett effektivt sätt utförligt verifiera all funktionalitet i designen. Ofta verifieras block först enskilt och sedan tillsammans med de andra blocken i kretsen. Många olika simulatorer och språk har utvecklats och förfinats för att möta behoven hos ingenjörer som utvecklar verifikationsmiljöer. SystemVerilog har blivit det dominerande språket men kompletteras oftast med en verifikations metodologi.
Det här arbete kommer att utveckla en ny verifieringsmiljö enligt Universal Verification Methodology (UVM) för att undersöka hur denna verifierings metodologi kan användas när olika separat utvecklade block ska verifieras tillsammans. Ett hårdvarublock i en grafisk processor kommer användas och UVM standarden kommer att analyseras utifrån hur den påverkar strukturen på verifieringsmiljön och dess prestanda. Det kommer resultera i ett antal riktlinjer för hur metodologin ska användas effektivt för block integrerande verifiering generellt och verifikation av grafiska processorer specifikt. (Less)
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/student-papers/record/9018284
- author
- Karlsson, Niklas LU
- supervisor
-
- Erik Larsson LU
- organization
- course
- EITM01 20201
- year
- 2020
- type
- H2 - Master's Degree (Two Years)
- subject
- report number
- LU/LTH-EIT 2020-766
- language
- English
- id
- 9018284
- date added to LUP
- 2020-06-24 15:53:51
- date last changed
- 2020-06-24 15:53:51
@misc{9018284,
abstract = {{The invention of the integrated circuit is a key milestone in the history of electronic circuits. Since its introduction the number of components on a chip have increased rapidly, making them more powerful and able to perform complex operations, but it has also changed the design process. Today different parts of a chip can be developed separately as Intellectual Property (IP) and then put together to form the final system.
Over the last years making sure that the design follows the specification, also known as functional verification, have become a key part of the development life cycle. Finding bugs early is crucial for keeping cost down and achieving time-to-market requirements. This means that as the complexity of the design continues to increase, the time needed to thoroughly verify it cannot follow the same line of increment. This has pushed engineers to come up with new tools and methodologies to improve the verification process.
The Universal Verification Methodology (UVM) is created by Accellera together with experts from electronic design automation vendors Synopsys, Mentor and Cadence. Its emphasis is on improving the development of verification environments by increasing interoperability and making it easier to reuse verification components.
This project will develop a new verification environment verification environment according to the Universal Verification Methodology to investigate how it can be implemented when separately developed blocks are verified together. A hardware block with sub-components from a Graphics Processing Unit (GPU) will be used and the methodology will be analysed based on how it affects the structure and performance of the verification environment. The dissertation will result in a new implemented verification environment along with guidelines on how to possibly improve block-integrating verification in general and verification of graphics processor specifically.}},
author = {{Karlsson, Niklas}},
language = {{eng}},
note = {{Student Paper}},
title = {{Development of a new verification environment for a GPU hardware block using the Universal Verification Methodology}},
year = {{2020}},
}