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Customization of Ibex RISC-V Processor Core

Raveendran, Rahul LU and Bhuinya, Subhajit LU (2021) In Customization of Ibex RISC-V Processor Core EITM02 20211
Department of Electrical and Information Technology
Abstract
Despite, the fact that we now have highly powerful and reliable CPU cores from System on Chip (SoC) Intellectual Property (IP) giants, the silicon industry is still leaning toward an efficient CPU core with an open-source Instruction Set Architecture (ISA) at the moment, where RISC-V has proven to be extremely successful. The aim to customize an open-source processor core, as described in our thesis subject, in order to find a cheaper alternative to high-priced CPU cores that can be tailored for specific applications is one of the key contribution of our thesis. It was anticipated that after customization, the Ibex core will perform
better, so we employed three reference algorithms to customize the Ibex Core. With a custom constructed... (More)
Despite, the fact that we now have highly powerful and reliable CPU cores from System on Chip (SoC) Intellectual Property (IP) giants, the silicon industry is still leaning toward an efficient CPU core with an open-source Instruction Set Architecture (ISA) at the moment, where RISC-V has proven to be extremely successful. The aim to customize an open-source processor core, as described in our thesis subject, in order to find a cheaper alternative to high-priced CPU cores that can be tailored for specific applications is one of the key contribution of our thesis. It was anticipated that after customization, the Ibex core will perform
better, so we employed three reference algorithms to customize the Ibex Core. With a custom constructed profiler, the goal was to discover the bottlenecks in the algorithm and build specific instructions to resolve them. Following that, we added custom instructions support to both software and hardware. Finally, after implementing custom instructions, hardware simulations were conducted and synthesis was performed. Post-customization results delivered on the expected promise by drastically reducing execution time while still maintaining a degree of hardware or gate count optimization. (Less)
Popular Abstract
The RISC-V Instruction Set Architecture (ISA) is a free and open standard based on Reduced Instruction Set Computer (RISC) concepts. The RISC-V ISA is free to use because it is distributed under open-source licenses that do not charge a fee. Through an open standard partnership, RISC-V has opened a new field of processor innovation. On core architectures, the RISC-V ISA provides a new level of open, extensible software and hardware flexibility, allowing implementation of custom instruction while retaining design innovation.
According to the current survey of the CPU industry, there are primarily two categories of CPU cores on the market. The first category uses an ISA that is licensed, such as cores from ARM, Intel etc which is typically... (More)
The RISC-V Instruction Set Architecture (ISA) is a free and open standard based on Reduced Instruction Set Computer (RISC) concepts. The RISC-V ISA is free to use because it is distributed under open-source licenses that do not charge a fee. Through an open standard partnership, RISC-V has opened a new field of processor innovation. On core architectures, the RISC-V ISA provides a new level of open, extensible software and hardware flexibility, allowing implementation of custom instruction while retaining design innovation.
According to the current survey of the CPU industry, there are primarily two categories of CPU cores on the market. The first category uses an ISA that is licensed, such as cores from ARM, Intel etc which is typically expensive to purchase and the second category of CPU cores that are attempting to revolutionize the semiconductor industry by using an open-source RISC-V ISA that would be both freely available and customizable. This thesis aims to customize Ibex, a lowRISC processor core that runs on RISC-V ISA, demonstrating the RISC-V ISA’s groundbreaking features while also proving to be a great alternative for simple, smaller applications. Ibex is a parameterizable open-source 32-bit RISC-V CPU core that is good for embedded applications. It is focused on hardware designers who want to integrate Ibex into their designs, as well as software developers who would like to create software running on Ibex. Since Ibex is open source, any Ibex user is encouraged to explore how the Ibex core can be used in their design and thus contribute to the open-source silicon development process. The Ibex core can be incorporated into any design that requires a compact, simple, and high-performance open-source processor core. (Less)
Please use this url to cite or link to this publication:
author
Raveendran, Rahul LU and Bhuinya, Subhajit LU
supervisor
organization
course
EITM02 20211
year
type
H2 - Master's Degree (Two Years)
subject
publication/series
Customization of Ibex RISC-V Processor Core
report number
LU/LTH-EIT 2021-830
language
English
id
9059569
date added to LUP
2021-06-29 11:22:58
date last changed
2021-06-29 11:22:58
@misc{9059569,
  abstract     = {{Despite, the fact that we now have highly powerful and reliable CPU cores from System on Chip (SoC) Intellectual Property (IP) giants, the silicon industry is still leaning toward an efficient CPU core with an open-source Instruction Set Architecture (ISA) at the moment, where RISC-V has proven to be extremely successful. The aim to customize an open-source processor core, as described in our thesis subject, in order to find a cheaper alternative to high-priced CPU cores that can be tailored for specific applications is one of the key contribution of our thesis. It was anticipated that after customization, the Ibex core will perform
better, so we employed three reference algorithms to customize the Ibex Core. With a custom constructed profiler, the goal was to discover the bottlenecks in the algorithm and build specific instructions to resolve them. Following that, we added custom instructions support to both software and hardware. Finally, after implementing custom instructions, hardware simulations were conducted and synthesis was performed. Post-customization results delivered on the expected promise by drastically reducing execution time while still maintaining a degree of hardware or gate count optimization.}},
  author       = {{Raveendran, Rahul and Bhuinya, Subhajit}},
  language     = {{eng}},
  note         = {{Student Paper}},
  series       = {{Customization of Ibex RISC-V Processor Core}},
  title        = {{Customization of Ibex RISC-V Processor Core}},
  year         = {{2021}},
}