Ethernet DMA Datapath Performance Optimization for 5G Radios

Abstract

Direct Memory Access (DMA) is a feature of computer systems that allows hardware subsystems to access the main memory of the system independent of the
Central Processing Unit (CPU). With the rise of big data transfers from/to different I/O devices, the use of DMA controllers has increased significantly. The
work of DMA is not limited to only offloading processor data transfer tasks, but it
can transfer data at much higher rates than processor reads and writes. ScatterGather DMA further enhances this technique by providing data transfers from
one non-contiguous block of memory to another by means of a series of smaller
contiguous-block transfers unlike normal DMA.

This thesis project explores Ericsson’s Ethernet DMA, which is used in the 5G
radios for high speed Ethernet data transfer. The ASIC hardware design was
synthesized and programmed on Intel’s Agilex development board. A test case
has been written to measure the performance of Ethernet DMA’s datapath. The
test case was run first to check the functionality of the design in a loop-back
scenario. A packet generator module was integrated to generate ethernet packets in the Ethernet DMA and the packets were sent through the datapath to be
written to the memory. Besides, ethernet packets were read from the memory
and transmitted from memory-mapped to streaming path. The performance of
Ethernet DMA datapath was measured for both streaming to memory-mapped
and memory-mapped to streaming paths. To get more reliable results, performance was measured directly from the design hardware using oscilloscope. The
obtained results are analyzed and some suggestions are proposed to optimize the
performance of Ethernet DMA.

Popular Abstract

With the advent of 5G wireless communication, the data rate will increase potentially (Gbps order), with low latency, and better quality of service (QoS) to
the users compared to previous generation cellular networks. CPU performances
and storage capacity has also increased with the miniaturization of the devices
and technological advancement. We are transferring more and more data in the
system, which is taking a big percentage of CPU usage. In modern processors,
more energy is consumed in moving data than on computational tasks.

To lessen the workload of the CPU, some tasks can be performed with the help of
supporting controllers. For example, we are using more and more Graphic Processing Units (GPUs) for the graphics processing tasks, and Google launched Tensor
Processing Unit (TPU) in 2016 for the dedicated computations involving machine
learning applications. Similarly, to transfer the data between the peripherals and
the memory, Direct Memory Access Controller (DMAC) was introduced to offload
the CPU from data transfer tasks. DMAC helps the system by doing the dedicated
task of the data transfer so that the CPU can focus on other tasks.

Ethernet is a wired computer networking technology which is commonly used in
local area networks (LAN), metropolitan area networks (MAN) and wide area networks (WAN). Owing to its adaptability to new requirements, Ethernet succeeded
to become dominant LAN technology and its data transfer rate has increased significantly over the years, starting from 2.94 Mbps to 400 Gbps.

The advancement in chip design has integrated the system with the network and
all the peripherals on a single chip. More and more dedicated hardware is being
developed for application specific tasks to increase the performance of the modern
systems. Ethernet DMA controller is a dedicated hardware used to transfer Ethernet data packets with much higher speed than a normal processor.

This thesis work studies Ericsson’s Ethernet DMA controller and measures its performance. The Ethernet DMA uses scatter-gather direct memory access (SGDMA)
technique which allows data transfer of data that can be written to non-contiguous
areas of memory. With this mechanism, it can perform transaction using buffer descriptors which can be placed in memory. As a result, high performance is achieved using scatter-gather DMA. A test case written in C language is used to measure the performance of Ethernet DMA’s datatapath by sending 10,000 ethernet packets of different packet sizes. The measurements are taken from real hardware using oscilloscope and the results presented show that the Ethernet DMA is configured to work at optimal performance. Based on the results obtained for the performance of Ethernet DMA controller, improvements have been suggested to further
increase its performance.

• author: Balathandapani, Saranya and Nanjiani, Sunil
• supervisor: Steffen Malkowsky
• organization: Department of Electrical and Information Technology
• course: EITM02 20211
• year: 2021
• type: H2 - Master's Degree (Two Years)
• subject: Technology and Engineering
• keywords: DMA, Ethernet DMA
• report number: LU/LTH-EIT 2021-833
• language: English
• id: 9060558
• date added to LUP: 2021-07-05 09:50:22
• date last changed: 2021-07-05 09:50:22