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Design parameterizable filter using High Level Synthesis

Folke, Troels Maehl LU and Ding, Wenqian LU (2021) EITM02 20211
Department of Electrical and Information Technology
Abstract (Swedish)
As the ASIC designs continue to grow in complexity, traditional RTL level of
abstraction is becoming a productivity bottleneck. The RTL design process requires extensive time and effort for verification of algorithmic correctness as well
as correct timing and interface behavior. Furthermore, a non-trivial change to the
algorithm often results in a complete rewrite of the RTL implementation. High
Level Synthesis (HLS) solves this issue, by allowing the designer to focus on the
functionality while the tool takes care of implementation details such as finite state
machines and timing. HLS vendors promise considerable savings in development
time.
In this master’s project, we have implemented a template of parameterizable
polyphase... (More)
As the ASIC designs continue to grow in complexity, traditional RTL level of
abstraction is becoming a productivity bottleneck. The RTL design process requires extensive time and effort for verification of algorithmic correctness as well
as correct timing and interface behavior. Furthermore, a non-trivial change to the
algorithm often results in a complete rewrite of the RTL implementation. High
Level Synthesis (HLS) solves this issue, by allowing the designer to focus on the
functionality while the tool takes care of implementation details such as finite state
machines and timing. HLS vendors promise considerable savings in development
time.
In this master’s project, we have implemented a template of parameterizable
polyphase filters in C++. The design was then synthesized using Mentor Catapult HLS. The number of polyphases, bitwidth, number of taps, and coefficient
binding were made parameterizable.
Simulation and verification results show the functional correctness of the design.
Also, a thorough comparison of the RTL reference design and an equivalent HLS
design, using the same parameter set, has been carried out. Results reveal that
the HLS design achieves higher performance in both area and latency. Taking the
symmetric FIR filter as an example, the latency is reduced by up to 5 clock cycles,
and the area decreased 21% compared to the reference design. The main reason
for reduction in latency and area is the ability of HLS tool to reduce and balance
the pipeline stages more efficiently compared to the manual RTL design. (Less)
Please use this url to cite or link to this publication:
author
Folke, Troels Maehl LU and Ding, Wenqian LU
supervisor
organization
course
EITM02 20211
year
type
H2 - Master's Degree (Two Years)
subject
report number
LU/LTH-EIT 2021-845
language
English
id
9065428
date added to LUP
2021-10-01 10:26:59
date last changed
2021-10-01 10:26:59
@misc{9065428,
  abstract     = {{As the ASIC designs continue to grow in complexity, traditional RTL level of
abstraction is becoming a productivity bottleneck. The RTL design process requires extensive time and effort for verification of algorithmic correctness as well
as correct timing and interface behavior. Furthermore, a non-trivial change to the
algorithm often results in a complete rewrite of the RTL implementation. High
Level Synthesis (HLS) solves this issue, by allowing the designer to focus on the
functionality while the tool takes care of implementation details such as finite state
machines and timing. HLS vendors promise considerable savings in development
time.
In this master’s project, we have implemented a template of parameterizable
polyphase filters in C++. The design was then synthesized using Mentor Catapult HLS. The number of polyphases, bitwidth, number of taps, and coefficient
binding were made parameterizable.
Simulation and verification results show the functional correctness of the design.
Also, a thorough comparison of the RTL reference design and an equivalent HLS
design, using the same parameter set, has been carried out. Results reveal that
the HLS design achieves higher performance in both area and latency. Taking the
symmetric FIR filter as an example, the latency is reduced by up to 5 clock cycles,
and the area decreased 21% compared to the reference design. The main reason
for reduction in latency and area is the ability of HLS tool to reduce and balance
the pipeline stages more efficiently compared to the manual RTL design.}},
  author       = {{Folke, Troels Maehl and Ding, Wenqian}},
  language     = {{eng}},
  note         = {{Student Paper}},
  title        = {{Design parameterizable filter using High Level Synthesis}},
  year         = {{2021}},
}