Automated Layout Porting and Optimization of digital designs
(2021) EITM02 20211Department of Electrical and Information Technology
- Abstract
- The aim of the thesis is to investigate and implement an algorithm that can automate the porting of the layout from one technology node to another technology
node. The layout optimization of any design block can be implemented for better performance. The primary task of the project is to develop a tool that can
optimize and port the complete layout design that reduces the time and effort of manual work. The optimization algorithm is tested for each block of the design and nearly 90% of the design is DRC clean. The porting of any design blocks is also implemented and it has been tested for any DRC issues. By modifying the
length and width of the design blocks using the tool, the analog layout can be generated in less time based on the... (More) - The aim of the thesis is to investigate and implement an algorithm that can automate the porting of the layout from one technology node to another technology
node. The layout optimization of any design block can be implemented for better performance. The primary task of the project is to develop a tool that can
optimize and port the complete layout design that reduces the time and effort of manual work. The optimization algorithm is tested for each block of the design and nearly 90% of the design is DRC clean. The porting of any design blocks is also implemented and it has been tested for any DRC issues. By modifying the
length and width of the design blocks using the tool, the analog layout can be generated in less time based on the design requirements. For each block of design,
the pitch distance between the two poly-silicon was also modified so that we can generate the layout of the design for different process nodes. (Less)
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/student-papers/record/9066526
- author
- Shekar, Karthik Srinivasan LU
- supervisor
- organization
- course
- EITM02 20211
- year
- 2021
- type
- H2 - Master's Degree (Two Years)
- subject
- report number
- LU/LTH-EIT 2021-846
- language
- English
- id
- 9066526
- date added to LUP
- 2021-11-01 11:08:33
- date last changed
- 2021-11-01 11:08:33
@misc{9066526, abstract = {{The aim of the thesis is to investigate and implement an algorithm that can automate the porting of the layout from one technology node to another technology node. The layout optimization of any design block can be implemented for better performance. The primary task of the project is to develop a tool that can optimize and port the complete layout design that reduces the time and effort of manual work. The optimization algorithm is tested for each block of the design and nearly 90% of the design is DRC clean. The porting of any design blocks is also implemented and it has been tested for any DRC issues. By modifying the length and width of the design blocks using the tool, the analog layout can be generated in less time based on the design requirements. For each block of design, the pitch distance between the two poly-silicon was also modified so that we can generate the layout of the design for different process nodes.}}, author = {{Shekar, Karthik Srinivasan}}, language = {{eng}}, note = {{Student Paper}}, title = {{Automated Layout Porting and Optimization of digital designs}}, year = {{2021}}, }