Study of Monitoring Circuitry for Ageing in FPGAs

Abstract

Along with the down-scaling of CMOS technology, ageing has become one of the most important reliability challenges in CMOS devices. Ageing is defined as degradation in certain device characteristics such as delay, which can result in failure. Field Programmable Gate Arrays (FPGAs) are typically the first among the CMOS devices to adopt the latest technology. It is, therefore, crucial to tackle ageing in FPGAs. As design-time-only techniques might prove insufficient in providing enough margins for future CMOS technology nodes, it becomes important to also monitor for the ageing degree to ensure the correct functionality.

This thesis aims to review previous work to understand ageing and find effective ageing monitoring methods for FPGAs, in terms of the ability to detect degradation of the fabric resources with high accuracy and high precision. A comprehensive survey of previous methods is conducted, reporting a comparison of monitors in detail and comparing their pros and cons. Based on the survey, we perceived the process/performance variation mapping method by use of ring-oscillators (the so-called PV mapping) to have great potential and enhanced the existing PV mapping method by (1) introducing sensors based on new ring-oscillator types that cover significantly more hardware resources, and thus enhance the monitoring coverage, (2) pushing the number of uniform sensors (each sensor being comprised of a ring oscillator and a frequency counter) by the use of carefully developed placement constraints to almost 80% of the maximum theoretically possible number of sensors of the suggested type, and (3) designing extra ring-oscillator types and circuitry for gaining more insights into the precision and coverage of the proposed performance variation (PV) mapping method. The PV mapping method was applied to 20 Digilent Nexys4 boards, featuring a 28nm XILINX ARTIX 7 XC7A100T FPGAs to validate that the proposed method is capable of detecting delay differences among uniformly shaped sensors on the same device, and for each sensor among multiple boards. In addition, the precision and accuracy of the proposed method are reported.

Popular Abstract

We use electronic systems everyday as they are present in computers, phones, home appliances, cars, etc. Electronic systems are made of small components called chips, and the chips are made of up to billions of nano-scale components called transistors, which are connected with nano-scale wires. The transistors and wires inside a chip are subject to a phenomenon called ageing, which results in the degradation of their functionality. For example, an aged chip cannot perform as fast as when it was new, resulting in malfunctioning. Up until now, to avoid such degradation due to ageing, the systems designers added a lot of performance margin so that even if the chip is affected by ageing, it could still continue working with the intended performance for the intended life-cycle. However, since in the future, due to the need for more performance and lower power consumption, more and smaller transistors should be used. Designing with such extra margins for future technology is going to be too costly. One solution, would be to monitor the chips for ageing and take action, such as replacement, before the chip malfunctions. For monitoring, typically, designers need to integrate monitoring sensors with the circuits inside the chips, which takes some design effort and also requires resources in terms of transistors and wires.

This thesis work looks into a class of chips called FPGAs. FPGAs are programmable, meaning that after they are manufactured, one can program their internal circuitry many times to carry out different functions. In this thesis work, we take advantage of this programmability to perform monitoring for ageing. The advantage with this method is that the designers can save both design efforts and programmable resources by avoiding integrating the monitoring sensors directly into their designs, and instead design one program just for monitoring.

We place a certain number of sensors on the FPGA board, and the frequency reported by the sensor is used as the indicator for ageing. If the sensor frequency is lower than the minimum acceptable value, the chip is judged to have aged too much. We will periodically measure and collect the results of the sensors to monitor aging by observing whether they are close to the minimum acceptable value. We have performed extensive experiments with our monitoring method, and have shown that with our method it is possible to detect subtle frequency differences both between sensors inside the same FPGA, as well as between the same sensor location on different FPGAs. Based on this, we expect that this method will also be capable of detecting ageing (indicated by gradual changes in the frequencies reported by the sensors) and predicting malfunctions when sensor data is collected periodically throughout the lifetime of an FPGA.

• author: Cheng, Pengxiang
• supervisor: Erik Larsson
• organization: Department of Electrical and Information Technology
• course: EITM02 20202
• year: 2021
• type: H2 - Master's Degree (Two Years)
• subject: Technology and Engineering
• keywords: FPGAs, Ageing
• report number: LU/LTH-EIT 2021-851
• language: English
• id: 9068747
• date added to LUP: 2021-12-03 11:17:54
• date last changed: 2021-12-03 11:17:54