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D-band Power Amplifiers in Vertical InGaAs Nanowire MOSFET Technology for 100 Gbps Wireless Communication

Blomberg, Patrik LU and Pile, Ludvig LU (2022) EITM01 20221
Department of Electrical and Information Technology
Abstract
Two different topologies of power amplifiers (PAs) are designed in the frequency
range 130-174.8 GHz for use in backhaul transmitters. These are the pseudo-differential common source (PDCS) and the single-ended stacked amplifier topologies. The PAs are designed in Cadence AWR design environment with virtual
source models, implemented in Verilog-A, of InGaAs nanowire transistors using a
20 nm gate length. The results are compared amongst each other as well as with
other state-of-the-art PAs. The PDCS PA achieves a simulated gain of 24.1 dB,
a saturated output power (Psat) of 12.1 dBm, a maximum power-added efficiency
(PAEmax) of 9.8 % and an output power at the 1 dB compression point (P1dB)
of 8 dBm using a supply voltage of 0.81 V.... (More)
Two different topologies of power amplifiers (PAs) are designed in the frequency
range 130-174.8 GHz for use in backhaul transmitters. These are the pseudo-differential common source (PDCS) and the single-ended stacked amplifier topologies. The PAs are designed in Cadence AWR design environment with virtual
source models, implemented in Verilog-A, of InGaAs nanowire transistors using a
20 nm gate length. The results are compared amongst each other as well as with
other state-of-the-art PAs. The PDCS PA achieves a simulated gain of 24.1 dB,
a saturated output power (Psat) of 12.1 dBm, a maximum power-added efficiency
(PAEmax) of 9.8 % and an output power at the 1 dB compression point (P1dB)
of 8 dBm using a supply voltage of 0.81 V. The stacked PA achieves a gain of
18.9 dBm, Psat of 13.6 dBm, PAEmax of 14.6 % and P1dB of 10.4 dBm using a
supply voltage of 2.25 V. Additionally simulations using AWR Microwave Office
is performed to evaluate the system performance of the PAs when transmitting
at a data rate of 100 Gbps. The PDCS PA and stacked PA achieved a maximum
output power of 3.6 dbM and 6.5 dBm respectively at the error vector magnitude
(EVM) limit of 3.5 % for 256 QAM signals. For 64 QAM signals they achieved a
maximum output power of 6.5 and 8 dBm respectively at the EVM limit of 5.5
%. (Less)
Popular Abstract
As cellphones and computers are able to achieve a fast internet the need for faster communications might seem unnecessary to the average user. But as technology advances the amount of devices which use it increases, everything from household appliances to cars are becoming connected to the internet. While some applications are simple quality-of-life, improvements others may improve modern society, one example being autonomous driving cars. In an ideal world where all cars are autonomous and shared, the amount of cars could decrease significantly which in turn would open up space in urban environments. In this scenario the need for traffic lights would be eliminated, and while it may seem like a small change it could reduce the time it... (More)
As cellphones and computers are able to achieve a fast internet the need for faster communications might seem unnecessary to the average user. But as technology advances the amount of devices which use it increases, everything from household appliances to cars are becoming connected to the internet. While some applications are simple quality-of-life, improvements others may improve modern society, one example being autonomous driving cars. In an ideal world where all cars are autonomous and shared, the amount of cars could decrease significantly which in turn would open up space in urban environments. In this scenario the need for traffic lights would be eliminated, and while it may seem like a small change it could reduce the time it takes to travel by car. As well as reduce the environmental impact of having multiple cars in idle.

While the relatively newly launched fifth generation cellular network (5G) have
made improvements to the data rate, it is necessary to increase it further. Beyond 5G cellular networks are looking to expand the data rate by operating at higher frequencies than its predecessors. These frequencies are often referred to as mmWave frequencies. In wireless communication the data is sent with electromagnetic waves. The data rate is correlated with the bandwidth of the signal, the bandwidth being the span of frequencies that the signal covers. Higher frequency ranges has a greater amount of available bandwidth, which can be used to increase the data rate.

Higher frequencies do however pose a difficult task for the transistors. The scaling of transistors has shrunk them to a point where new transistor technologies are necessary. The vertical nanowire transistor is one technology which has a great performance and area-efficiency.

The power amplifier is the final stage before the antenna in a transmitter. It
amplifies the signal, with a larger output power of the signal it may travel further without being undetectable. However, careful design has to be performed to not destroy the shape of the signal in the process. In this thesis two different circuit architectures are designed using nanowire transistors, and then compared with other technologies to verify that the technology is competitive and suitable for high data rate communication at high frequencies. (Less)
Please use this url to cite or link to this publication:
author
Blomberg, Patrik LU and Pile, Ludvig LU
supervisor
organization
course
EITM01 20221
year
type
H2 - Master's Degree (Two Years)
subject
keywords
D-band, Power Amplifier, Pseudo-differential common source, Stacked, Vertical InGaAs nanowire, MOSFET
report number
LU/LTH-EIT 2022-867
language
English
id
9088150
date added to LUP
2022-06-21 10:59:53
date last changed
2022-06-21 10:59:53
@misc{9088150,
  abstract     = {{Two different topologies of power amplifiers (PAs) are designed in the frequency
range 130-174.8 GHz for use in backhaul transmitters. These are the pseudo-differential common source (PDCS) and the single-ended stacked amplifier topologies. The PAs are designed in Cadence AWR design environment with virtual
source models, implemented in Verilog-A, of InGaAs nanowire transistors using a
20 nm gate length. The results are compared amongst each other as well as with
other state-of-the-art PAs. The PDCS PA achieves a simulated gain of 24.1 dB,
a saturated output power (Psat) of 12.1 dBm, a maximum power-added efficiency
(PAEmax) of 9.8 % and an output power at the 1 dB compression point (P1dB)
of 8 dBm using a supply voltage of 0.81 V. The stacked PA achieves a gain of
18.9 dBm, Psat of 13.6 dBm, PAEmax of 14.6 % and P1dB of 10.4 dBm using a
supply voltage of 2.25 V. Additionally simulations using AWR Microwave Office
is performed to evaluate the system performance of the PAs when transmitting
at a data rate of 100 Gbps. The PDCS PA and stacked PA achieved a maximum
output power of 3.6 dbM and 6.5 dBm respectively at the error vector magnitude
(EVM) limit of 3.5 % for 256 QAM signals. For 64 QAM signals they achieved a
maximum output power of 6.5 and 8 dBm respectively at the EVM limit of 5.5
%.}},
  author       = {{Blomberg, Patrik and Pile, Ludvig}},
  language     = {{eng}},
  note         = {{Student Paper}},
  title        = {{D-band Power Amplifiers in Vertical InGaAs Nanowire MOSFET Technology for 100 Gbps Wireless Communication}},
  year         = {{2022}},
}