Skip to main content

LUP Student Papers

LUND UNIVERSITY LIBRARIES

FPGA implementation of an sEMG classifier

Marnfeldt, William LU (2022) BMEM01 20222
Department of Biomedical Engineering
Abstract
This master’s thesis discusses the implementation of a convolutional neural
network on a Field Programmable Gate Array (FPGA). It deals with implementation be describing a tool chain, starting with the designing of a model
in Keras, transforming the model to Hardware Descriptive Language, and
finally implementing it on an FPGA. Performance on three different scales
of the same model topology are compared, in the following terms: accuracy,
timing and power consumption. Findings show that timing is within acceptable ranges, with limitations lying in model capacity, and power consumption. Furthermore, the specific model is compared with a similar topology.
Finally, suggestions for future attempts are proposed, suggesting new layer
... (More)
This master’s thesis discusses the implementation of a convolutional neural
network on a Field Programmable Gate Array (FPGA). It deals with implementation be describing a tool chain, starting with the designing of a model
in Keras, transforming the model to Hardware Descriptive Language, and
finally implementing it on an FPGA. Performance on three different scales
of the same model topology are compared, in the following terms: accuracy,
timing and power consumption. Findings show that timing is within acceptable ranges, with limitations lying in model capacity, and power consumption. Furthermore, the specific model is compared with a similar topology.
Finally, suggestions for future attempts are proposed, suggesting new layer
types. (Less)
Popular Abstract
Can artificial neural networks be deployed on FPGAs for prosthesis control?

With FPGAs, custom hardware can be designed for artificial neural net-
works. This may lead to performance improvements for artificial neural
networks, thereby allowing for more advanced prosthesis control.

For an amputee, a comfortable and easily controllable robotic prosthesis may significantly improve life quality. One of the proposed inputs for controlling robotic prostheses is by surface electromyography. In other words, the prosthesis can be controlled by measuring the electrical potential in muscles from the surface of the skin. A neural network can then be trained to infer movement patterns from these signals. An issue with neural networks is their... (More)
Can artificial neural networks be deployed on FPGAs for prosthesis control?

With FPGAs, custom hardware can be designed for artificial neural net-
works. This may lead to performance improvements for artificial neural
networks, thereby allowing for more advanced prosthesis control.

For an amputee, a comfortable and easily controllable robotic prosthesis may significantly improve life quality. One of the proposed inputs for controlling robotic prostheses is by surface electromyography. In other words, the prosthesis can be controlled by measuring the electrical potential in muscles from the surface of the skin. A neural network can then be trained to infer movement patterns from these signals. An issue with neural networks is their large complexity, making them difficult to adopt on smaller microcontrollers, typically desired on prostheses that run on battery. This puts a limit on the scale and speed of the neural networks that can be deployed. A good prosthesis controller should not only correctly determine the intended movement, but also do it within a short time frame. For this reason, the alternative approach of using FPGAs was attempted. An FPGA is in essence re-configurable hardware, where instead of programming software into hardware, the hardware itself is programmed. This allows task specific hardware to be built which can do many calculations at once. In short, the main advantage would be allowing for multiple calculations to be performed in parallel as opposed to in a sequence, thus gaining a speedup. A workflow was proposed and followed in which a Convolutional Neural Network was constructed and trained on a computer. It was then, through several steps, translated into a corresponding hardware design, and deployed to an FPGA. The resulting implementation was fast enough to allow for multiple inferences within the desired timing constraint. This, in turn, meant that majority voting could be used to improve results. There still remain issues, notably in accuracy and power consumption. Overall, this project successfully demonstrated the possibility of using FPGAs as controllers. In the future, this may open up for possibilities of using more dedicated hardware for neural networks, with FPGAs acting as design prototypes. (Less)
Please use this url to cite or link to this publication:
author
Marnfeldt, William LU
supervisor
organization
alternative title
Ytelektromyografisk klassificerare implementerad på en FPGA
course
BMEM01 20222
year
type
H2 - Master's Degree (Two Years)
subject
keywords
electromyography, convolutional neural networks, classifier, field programmable gate array, prosthetic hand
language
English
additional info
2022-23
id
9104186
date added to LUP
2023-02-17 15:07:50
date last changed
2023-02-17 15:07:50
@misc{9104186,
  abstract     = {{This master’s thesis discusses the implementation of a convolutional neural
network on a Field Programmable Gate Array (FPGA). It deals with implementation be describing a tool chain, starting with the designing of a model
in Keras, transforming the model to Hardware Descriptive Language, and
finally implementing it on an FPGA. Performance on three different scales
of the same model topology are compared, in the following terms: accuracy,
timing and power consumption. Findings show that timing is within acceptable ranges, with limitations lying in model capacity, and power consumption. Furthermore, the specific model is compared with a similar topology.
Finally, suggestions for future attempts are proposed, suggesting new layer
types.}},
  author       = {{Marnfeldt, William}},
  language     = {{eng}},
  note         = {{Student Paper}},
  title        = {{FPGA implementation of an sEMG classifier}},
  year         = {{2022}},
}