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Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures

Wolinski, Christophe ; Kuchcinski, Krzysztof LU orcid ; Teich, Jürgen and Hannig, Frank (2008) International Conference on Field Programmable Logic and Applications (FPL) p.391-396
Abstract
n this paper, we introduce a constraint programming-based approach for the optimization of area and of reconfiguration time for communication networks for a class of regular 2D reconfigurable processor array architectures. For a given set of different algorithms the execution of which is supposed to be switched upon request at run-time, we provide static solutions for the optimal routing of data between processors. Here, we support also multi-casting data transfers for the first time. The routing found by our method minimizes the area or the reconfiguration time of the communication network, when switching between the execution of these algorithms. In fact, when switching, the communication network reconfiguration can be executed in just a... (More)
n this paper, we introduce a constraint programming-based approach for the optimization of area and of reconfiguration time for communication networks for a class of regular 2D reconfigurable processor array architectures. For a given set of different algorithms the execution of which is supposed to be switched upon request at run-time, we provide static solutions for the optimal routing of data between processors. Here, we support also multi-casting data transfers for the first time. The routing found by our method minimizes the area or the reconfiguration time of the communication network, when switching between the execution of these algorithms. In fact, when switching, the communication network reconfiguration can be executed in just a few clock cycles. Moreover the communication network area can be minimized significantly (62% in average). (Less)
Please use this url to cite or link to this publication:
author
; ; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
host publication
2008 International Conference on Field Programmable Logic and Applications
pages
6 pages
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
International Conference on Field Programmable Logic and Applications (FPL)
conference location
Heidelberg, Germany
conference dates
2008-09-08 - 2008-09-10
external identifiers
  • scopus:54949147305
ISBN
978-1-4244-1960-9
DOI
10.1109/FPL.2008.4629969
language
English
LU publication?
yes
id
0cdc2fd1-e40e-4039-8551-995efe96957f (old id 1151638)
date added to LUP
2016-04-04 14:27:59
date last changed
2022-02-01 20:31:46
@inproceedings{0cdc2fd1-e40e-4039-8551-995efe96957f,
  abstract     = {{n this paper, we introduce a constraint programming-based approach for the optimization of area and of reconfiguration time for communication networks for a class of regular 2D reconfigurable processor array architectures. For a given set of different algorithms the execution of which is supposed to be switched upon request at run-time, we provide static solutions for the optimal routing of data between processors. Here, we support also multi-casting data transfers for the first time. The routing found by our method minimizes the area or the reconfiguration time of the communication network, when switching between the execution of these algorithms. In fact, when switching, the communication network reconfiguration can be executed in just a few clock cycles. Moreover the communication network area can be minimized significantly (62% in average).}},
  author       = {{Wolinski, Christophe and Kuchcinski, Krzysztof and Teich, Jürgen and Hannig, Frank}},
  booktitle    = {{2008 International Conference on Field Programmable Logic and Applications}},
  isbn         = {{978-1-4244-1960-9}},
  language     = {{eng}},
  pages        = {{391--396}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures}},
  url          = {{http://dx.doi.org/10.1109/FPL.2008.4629969}},
  doi          = {{10.1109/FPL.2008.4629969}},
  year         = {{2008}},
}