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Compressed Level Crossing Sampling for Ultra-Low Power IoT Devices

Zhou, Jun ; Tofighi Zavareh, Amir ; Gupta, Robin ; Liu, Liang LU orcid ; Wang, Zhongfeng ; Sadler, Brian M. ; Silva-Martinez, Jose and Hoyos, Sebastian (2017) In IEEE Transactions on Circuits and Systems I: Regular Papers 64(9). p.2495-2507
Abstract

Level crossing sampling (LCS) is a power-efficient analog-to-digital conversion scheme for spikelike signals that arise in many Internet of Things-enabled automotive and environmental monitoring applications. However, LCS scheme requires a dedicated time-to-digital converter with large dynamic range specifications. In this paper, we present a compressed LCS that exploits the signal sparsity in the time domain. At the compressed sampling stage, a continuous-time ternary encoding scheme converts the amplitude variations into a ternary timing signal that is captured in a digital random sampler. At the reconstruction stage, a low-complexity split-projection least squares (SPLSs) signal reconstruction algorithm is presented. The SPLS splits... (More)

Level crossing sampling (LCS) is a power-efficient analog-to-digital conversion scheme for spikelike signals that arise in many Internet of Things-enabled automotive and environmental monitoring applications. However, LCS scheme requires a dedicated time-to-digital converter with large dynamic range specifications. In this paper, we present a compressed LCS that exploits the signal sparsity in the time domain. At the compressed sampling stage, a continuous-time ternary encoding scheme converts the amplitude variations into a ternary timing signal that is captured in a digital random sampler. At the reconstruction stage, a low-complexity split-projection least squares (SPLSs) signal reconstruction algorithm is presented. The SPLS splits random projections and utilizes a standard least squares approach that exploits the ternary-valued amplitude distribution. The SPLS algorithm is hardware friendly, can be run in parallel, and incorporates a low-cost k-term approximation scheme for matrix inversion. The SPLS hardware is analyzed, designed, and implemented in FPGA, achieving the highest data throughput and the power efficiency compared with the prior arts. Simulations of the proposed sampler in an automotive collision warning system demonstrate that the proposed compressed LCS can be very power efficient and robust to wireless interference, while achieving an approximately eightfold data volume compression when compared with Nyquist sampling approaches.

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author
; ; ; ; ; ; and
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
compressive sensing, Internet of Things, least squares, Level crossing sampling, sparse signal reconstruction.
in
IEEE Transactions on Circuits and Systems I: Regular Papers
volume
64
issue
9
pages
2495 - 2507
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:85021731581
  • wos:000409058000025
ISSN
1549-8328
DOI
10.1109/TCSI.2017.2707481
language
English
LU publication?
yes
id
0ededcae-8b09-4927-8b58-429c53a4777d
date added to LUP
2017-07-19 08:42:12
date last changed
2025-01-07 17:24:49
@article{0ededcae-8b09-4927-8b58-429c53a4777d,
  abstract     = {{<p>Level crossing sampling (LCS) is a power-efficient analog-to-digital conversion scheme for spikelike signals that arise in many Internet of Things-enabled automotive and environmental monitoring applications. However, LCS scheme requires a dedicated time-to-digital converter with large dynamic range specifications. In this paper, we present a compressed LCS that exploits the signal sparsity in the time domain. At the compressed sampling stage, a continuous-time ternary encoding scheme converts the amplitude variations into a ternary timing signal that is captured in a digital random sampler. At the reconstruction stage, a low-complexity split-projection least squares (SPLSs) signal reconstruction algorithm is presented. The SPLS splits random projections and utilizes a standard least squares approach that exploits the ternary-valued amplitude distribution. The SPLS algorithm is hardware friendly, can be run in parallel, and incorporates a low-cost k-term approximation scheme for matrix inversion. The SPLS hardware is analyzed, designed, and implemented in FPGA, achieving the highest data throughput and the power efficiency compared with the prior arts. Simulations of the proposed sampler in an automotive collision warning system demonstrate that the proposed compressed LCS can be very power efficient and robust to wireless interference, while achieving an approximately eightfold data volume compression when compared with Nyquist sampling approaches.</p>}},
  author       = {{Zhou, Jun and Tofighi Zavareh, Amir and Gupta, Robin and Liu, Liang and Wang, Zhongfeng and Sadler, Brian M. and Silva-Martinez, Jose and Hoyos, Sebastian}},
  issn         = {{1549-8328}},
  keywords     = {{compressive sensing; Internet of Things; least squares; Level crossing sampling; sparse signal reconstruction.}},
  language     = {{eng}},
  number       = {{9}},
  pages        = {{2495--2507}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  series       = {{IEEE Transactions on Circuits and Systems I: Regular Papers}},
  title        = {{Compressed Level Crossing Sampling for Ultra-Low Power IoT Devices}},
  url          = {{http://dx.doi.org/10.1109/TCSI.2017.2707481}},
  doi          = {{10.1109/TCSI.2017.2707481}},
  volume       = {{64}},
  year         = {{2017}},
}