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A low logic depth complex multiplier using distributed arithmetic

Berkeman, Anders ; Öwall, Viktor LU and Torkelson, Mats LU (2000) In IEEE Journal of Solid-State Circuits 35(4). p.656-659
Abstract
A combinatorial complex multiplier has been designed for use in a pipelined fast Fourier transform processor. The performance in terms of throughput of the processor is limited by the multiplication. Therefore, the multiplier is optimized to make the input-to-output delay as short as possible. A new architecture based on distributed arithmetic, Wallace-trees, and carry-lookahead adders has been developed. The multiplier has been fabricated using standard cells in a 0.5-μm process and verified for functionality, speed, and power consumption. Running at 40 MHz, a multiplier with input wordlengths of 16+16 times 10+10 bits consumes 54% less power compared to an distributed arithmetic array multiplier fabricated under equal conditions
Please use this url to cite or link to this publication:
author
; and
organization
publishing date
type
Contribution to journal
publication status
published
subject
in
IEEE Journal of Solid-State Circuits
volume
35
issue
4
pages
656 - 659
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:0347705168
ISSN
0018-9200
DOI
10.1109/4.839928
language
English
LU publication?
yes
id
3e93e9a7-0d96-4742-a75d-3143ee511f83 (old id 1036100)
date added to LUP
2016-04-01 16:30:48
date last changed
2022-01-28 20:12:23
@article{3e93e9a7-0d96-4742-a75d-3143ee511f83,
  abstract     = {{A combinatorial complex multiplier has been designed for use in a pipelined fast Fourier transform processor. The performance in terms of throughput of the processor is limited by the multiplication. Therefore, the multiplier is optimized to make the input-to-output delay as short as possible. A new architecture based on distributed arithmetic, Wallace-trees, and carry-lookahead adders has been developed. The multiplier has been fabricated using standard cells in a 0.5-μm process and verified for functionality, speed, and power consumption. Running at 40 MHz, a multiplier with input wordlengths of 16+16 times 10+10 bits consumes 54% less power compared to an distributed arithmetic array multiplier fabricated under equal conditions}},
  author       = {{Berkeman, Anders and Öwall, Viktor and Torkelson, Mats}},
  issn         = {{0018-9200}},
  language     = {{eng}},
  number       = {{4}},
  pages        = {{656--659}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  series       = {{IEEE Journal of Solid-State Circuits}},
  title        = {{A low logic depth complex multiplier using distributed arithmetic}},
  url          = {{https://lup.lub.lu.se/search/files/4695470/1580336.pdf}},
  doi          = {{10.1109/4.839928}},
  volume       = {{35}},
  year         = {{2000}},
}