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Design and measurement of a CT delta-sigma ADC with switched-capacitor switched-resistor feedback

Andersson, Martin LU and Sundström, Lars LU (2009) In IEEE Journal of Solid-State Circuits 44(2). p.473-483
Abstract
The performance of traditional continuous-time

(CT) delta-sigma analog-to-digital converters (ADCs) is

limited by their large sensitivity to feedback pulse-width variations

caused by clock jitter in their feedback digital-to-analog

converters (DACs). To mitigate that effect, we propose a modified

switched-capacitor (SC) feedback DAC technique, with a

variable switched series resistor (SR). The architecture has the

additional benefit of reducing the typically high SC DAC output

peak currents, resulting in reduced slew-rate requirements for the

loop-filter integrators. A theoretical investigation is carried out

which provides new insight into the... (More)
The performance of traditional continuous-time

(CT) delta-sigma analog-to-digital converters (ADCs) is

limited by their large sensitivity to feedback pulse-width variations

caused by clock jitter in their feedback digital-to-analog

converters (DACs). To mitigate that effect, we propose a modified

switched-capacitor (SC) feedback DAC technique, with a

variable switched series resistor (SR). The architecture has the

additional benefit of reducing the typically high SC DAC output

peak currents, resulting in reduced slew-rate requirements for the

loop-filter integrators. A theoretical investigation is carried out

which provides new insight into the synthesis of switched-capacitor

with switched series resistor (SCSR) DACs with a specified

reduction of the pulse-width jitter sensitivity and minimal power

consumption and complexity. To demonstrate the concept and to

verify the reduced pulse-width jitter sensitivity a 5 mW, 312 MHz,

second order, low-pass, 1-bit, CT delta-sigma modulator with SCSR

feedback was implemented in a 1.2 V, 90 nm, RF-CMOS process.

An SNR of 66.4 dB and an SNDR of 62.4 dB were measured

in a 1.92 MHz bandwidth. The sensitivity to wideband clock

phase noise was reduced by 30 dB compared to a traditional

switched-current (SI) return-to-zero (RZ) DAC. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
clock jitter, delta-sigma modulation, A/D conversion
in
IEEE Journal of Solid-State Circuits
volume
44
issue
2
pages
473 - 483
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • wos:000263032100015
  • scopus:59349110804
ISSN
0018-9200
DOI
10.1109/JSSC.2008.2010978
language
English
LU publication?
yes
id
fa759f02-c82b-4e3d-bbbf-e3587fcb2bba (old id 1037990)
date added to LUP
2008-02-27 12:13:05
date last changed
2017-09-10 04:19:15
@article{fa759f02-c82b-4e3d-bbbf-e3587fcb2bba,
  abstract     = {The performance of traditional continuous-time<br/><br>
(CT) delta-sigma analog-to-digital converters (ADCs) is<br/><br>
limited by their large sensitivity to feedback pulse-width variations<br/><br>
caused by clock jitter in their feedback digital-to-analog<br/><br>
converters (DACs). To mitigate that effect, we propose a modified<br/><br>
switched-capacitor (SC) feedback DAC technique, with a<br/><br>
variable switched series resistor (SR). The architecture has the<br/><br>
additional benefit of reducing the typically high SC DAC output<br/><br>
peak currents, resulting in reduced slew-rate requirements for the<br/><br>
loop-filter integrators. A theoretical investigation is carried out<br/><br>
which provides new insight into the synthesis of switched-capacitor<br/><br>
with switched series resistor (SCSR) DACs with a specified<br/><br>
reduction of the pulse-width jitter sensitivity and minimal power<br/><br>
consumption and complexity. To demonstrate the concept and to<br/><br>
verify the reduced pulse-width jitter sensitivity a 5 mW, 312 MHz,<br/><br>
second order, low-pass, 1-bit, CT delta-sigma modulator with SCSR<br/><br>
feedback was implemented in a 1.2 V, 90 nm, RF-CMOS process.<br/><br>
An SNR of 66.4 dB and an SNDR of 62.4 dB were measured<br/><br>
in a 1.92 MHz bandwidth. The sensitivity to wideband clock<br/><br>
phase noise was reduced by 30 dB compared to a traditional<br/><br>
switched-current (SI) return-to-zero (RZ) DAC.},
  author       = {Andersson, Martin and Sundström, Lars},
  issn         = {0018-9200},
  keyword      = {clock jitter,delta-sigma modulation,A/D conversion},
  language     = {eng},
  number       = {2},
  pages        = {473--483},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Journal of Solid-State Circuits},
  title        = {Design and measurement of a CT delta-sigma ADC with switched-capacitor switched-resistor feedback},
  url          = {http://dx.doi.org/10.1109/JSSC.2008.2010978},
  volume       = {44},
  year         = {2009},
}