CMOS AnalogtoDigital Converters  Analysis, Modeling, and Design
(2008) Abstract
 A highperformance and flexible analogtodigital converter (ADC), that can be integrated in deepsubmicron CMOS technology, is a key building block for reduced size, cost and power consumption of digital communication systems. This dissertation concerns the investigation of particular problems associated with the design of such ADCs.
The problem of increased clock jitter sensitivity of lowpass (LP), 1bit, continuoustime (CT) DeltaSigma modulators with returntozero (RZ) feedback is studied. A highlevel behavioral model is developed that can be used to simulate the dominant clock phase noise effects, with arbitrary clock phase noise and input signals, quickly and accurately. The accuracy of the presented model is... (More)  A highperformance and flexible analogtodigital converter (ADC), that can be integrated in deepsubmicron CMOS technology, is a key building block for reduced size, cost and power consumption of digital communication systems. This dissertation concerns the investigation of particular problems associated with the design of such ADCs.
The problem of increased clock jitter sensitivity of lowpass (LP), 1bit, continuoustime (CT) DeltaSigma modulators with returntozero (RZ) feedback is studied. A highlevel behavioral model is developed that can be used to simulate the dominant clock phase noise effects, with arbitrary clock phase noise and input signals, quickly and accurately. The accuracy of the presented model is verified by measurements on a second order LP CT DeltaSigma modulator circuit with switched current (SI) RZ feedback digitaltoanalog converter (DAC). As part of the verification a simulation and measurement technique is developed that enables studies of the clock phase noise sensitivity for different frequency offsets separately. It is found by simulations that the wideband clock phase noise, modulating the amount of charge delivered, per clock period, by the traditional SI (RZ) feedback DAC, is the dominating effect in many practical situations. To reduce the sensitivity to wideband clock phase noise, a switchedcapacitor switchedresistor (SCSR) feedback DAC concept is proposed, which makes the amount of charge per clock period less dependent on the exact timing of the clock edges. The architecture has the additional benefit of reducing the typically high SC DAC output peak currents, resulting in reduced slewrate requirements for the loopfilter integrator(s). A functional level analysis of the tradeoffs between the reduction of the pulsewidth jitter sensitivity, the DAC output peak current and the SC discharge time constant is carried out. To demonstrate the concept and to verify the reduced pulsewidth jitter sensitivity a 5mW, 312MHz, second order, LP, 1bit, CT DeltaSigma modulator with SCSR feedback has been implemented in a 1.2V 90nm RFCMOS process. A signaltonoise ratio (SNR) of 66.4dB and a signaltonoiseanddistortionratio (SNDR) of 62.4dB is measured in a 1.92MHz bandwidth. The measurements show that the sensitivity to wideband clock phase noise is reduced by 30dB compared to a traditional SI (RZ) DAC.
Additionally, the problems with offset and gain mismatch between the ADC units in a randomly timeinterleaved successiveapproximation (SA) ADC system is studied by measurements of a 12bit, 30MSPS, randomly timeinterleaved SAADC circuit. The effectiveness of previously presented error estimation and equalization algorithms is verified using the measured data, through an SNDR improvement of more than 10dB after error equalization.
Moreover, a sampling rate and resolution reconfigurable pipeline/cyclic ADC is proposed. Circuit techniques developed to enable the reconfiguration is presented. A 10bit 80MSPS pipeline/cyclic ADC, with 8 configurations, has been implemented in a 0.18um CMOS process. The ADC performance is verified by measurements. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/1148214
 author
 Andersson, Martin ^{LU}
 supervisor

 Jiren Yuan ^{LU}
 opponent

 Prof. Maloberti, Franco, University of Pavia, Italy
 organization
 publishing date
 2008
 type
 Thesis
 publication status
 published
 subject
 defense location
 Room E:1406, Ebuilding, Ole Römers väg 3, Lund university, Faculty of Engineering
 defense date
 20080605 13:15:00
 language
 English
 LU publication?
 yes
 id
 ece81feb2472455cab0feb133d695a4c (old id 1148214)
 date added to LUP
 20160404 09:21:10
 date last changed
 20181121 20:52:30
@phdthesis{ece81feb2472455cab0feb133d695a4c, abstract = {{A highperformance and flexible analogtodigital converter (ADC), that can be integrated in deepsubmicron CMOS technology, is a key building block for reduced size, cost and power consumption of digital communication systems. This dissertation concerns the investigation of particular problems associated with the design of such ADCs. <br/><br> <br/><br> The problem of increased clock jitter sensitivity of lowpass (LP), 1bit, continuoustime (CT) DeltaSigma modulators with returntozero (RZ) feedback is studied. A highlevel behavioral model is developed that can be used to simulate the dominant clock phase noise effects, with arbitrary clock phase noise and input signals, quickly and accurately. The accuracy of the presented model is verified by measurements on a second order LP CT DeltaSigma modulator circuit with switched current (SI) RZ feedback digitaltoanalog converter (DAC). As part of the verification a simulation and measurement technique is developed that enables studies of the clock phase noise sensitivity for different frequency offsets separately. It is found by simulations that the wideband clock phase noise, modulating the amount of charge delivered, per clock period, by the traditional SI (RZ) feedback DAC, is the dominating effect in many practical situations. To reduce the sensitivity to wideband clock phase noise, a switchedcapacitor switchedresistor (SCSR) feedback DAC concept is proposed, which makes the amount of charge per clock period less dependent on the exact timing of the clock edges. The architecture has the additional benefit of reducing the typically high SC DAC output peak currents, resulting in reduced slewrate requirements for the loopfilter integrator(s). A functional level analysis of the tradeoffs between the reduction of the pulsewidth jitter sensitivity, the DAC output peak current and the SC discharge time constant is carried out. To demonstrate the concept and to verify the reduced pulsewidth jitter sensitivity a 5mW, 312MHz, second order, LP, 1bit, CT DeltaSigma modulator with SCSR feedback has been implemented in a 1.2V 90nm RFCMOS process. A signaltonoise ratio (SNR) of 66.4dB and a signaltonoiseanddistortionratio (SNDR) of 62.4dB is measured in a 1.92MHz bandwidth. The measurements show that the sensitivity to wideband clock phase noise is reduced by 30dB compared to a traditional SI (RZ) DAC.<br/><br> <br/><br> Additionally, the problems with offset and gain mismatch between the ADC units in a randomly timeinterleaved successiveapproximation (SA) ADC system is studied by measurements of a 12bit, 30MSPS, randomly timeinterleaved SAADC circuit. The effectiveness of previously presented error estimation and equalization algorithms is verified using the measured data, through an SNDR improvement of more than 10dB after error equalization.<br/><br> <br/><br> Moreover, a sampling rate and resolution reconfigurable pipeline/cyclic ADC is proposed. Circuit techniques developed to enable the reconfiguration is presented. A 10bit 80MSPS pipeline/cyclic ADC, with 8 configurations, has been implemented in a 0.18um CMOS process. The ADC performance is verified by measurements.}}, author = {{Andersson, Martin}}, language = {{eng}}, school = {{Lund University}}, title = {{CMOS AnalogtoDigital Converters  Analysis, Modeling, and Design}}, url = {{https://lup.lub.lu.se/search/files/5301101/1148315.pdf}}, year = {{2008}}, }