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Design of Reconfigurable Hardware Architectures for Real-time Applications

Lenart, Thomas LU (2008) In Series of licentiate and doctoral thesis 5.
Abstract
This thesis discusses modeling and implementation of reconfigurable hardware

architectures for real-time applications. The target application in this work

is digital holographic imaging, where visible images are to be reconstructed

based on holographic recordings. The reconstruction process is computationally

demanding and requires hardware acceleration to achieve real-time performance.

Thus, this work presents two design approaches, with different levels

of reconfigurability, to accelerate the image reconstruction process and related

computationally demanding applications.



The first approach is based on application-specific hardware accelerators,... (More)
This thesis discusses modeling and implementation of reconfigurable hardware

architectures for real-time applications. The target application in this work

is digital holographic imaging, where visible images are to be reconstructed

based on holographic recordings. The reconstruction process is computationally

demanding and requires hardware acceleration to achieve real-time performance.

Thus, this work presents two design approaches, with different levels

of reconfigurability, to accelerate the image reconstruction process and related

computationally demanding applications.



The first approach is based on application-specific hardware accelerators, which

are usually required in systems with high constraints on processing performance,

physical size, or power consumption, and are tailored for a certain

application to achieve high performance. Hence, an acceleration platform

is proposed and designed to enable real-time image reconstruction in digital

holographic imaging, constituting a set of hardware accelerators that are connected

in a flexible and reconfigurable pipeline. Hardware accelerators are

optimized for high computational performance and low memory requirements.

The application-specific design has been integrated into an embedded system

consisting of a microprocessor, a high-performance memory controller, a digital

image sensor, and a video output device. The system has been prototyped

using an FPGA platform and synthesized for a 0.13 μm standard cell library,

achieving a reconstruction rate of 30 frames per second running at 400 MHz.



The second approach is based on a dynamically reconfigurable architecture

to accelerate arbitrary applications, which presents a trade-off between versatileness

and hardware cost. The proposed reconfigurable architecture is constructed

from processing and memory cells, which communicate using a combination

of local interconnects and a global network. High-performance local

interconnects generate a high communication bandwidth between neighboring

cells, while the global network provides flexibility and access to external memory.

The processing and memory cells are run-time reconfigurable to enable

flexible application mapping. Proposed reconfigurable architectures are modeled

and evaluated using Scenic, which is a system-level exploration environment

developed in this work. A design with 16 cells is implemented and synthesized

for a 0.13 μm standard cell library, resulting in low area overhead when

compared with application-specific solutions. It is shown that the proposed

reconfigurable architecture achieves high computation performance compared

to traditional DSP processors. (Less)
Please use this url to cite or link to this publication:
author
supervisor
opponent
  • Prof. Dr.-Ing. Teich, Jürgen, University of Erlangen-Nuremberg,Germany
organization
publishing date
type
Thesis
publication status
published
subject
keywords
Stream Processing, Digital Holography, Reconfigurable Computing, Reconfigurable Architectures, Run-time Reconfiguration, Design Exploration, Hybrid floating-point, Data Scaling, FFT, ASIC
in
Series of licentiate and doctoral thesis
volume
5
pages
175 pages
publisher
The Department of Electrical and Information Technology
defense location
Room E:1406, E-building, Ole Römers väg 3, Lund university Faculty of Engineering
defense date
2008-06-03 09:15
ISSN
1654-790X
language
English
LU publication?
yes
id
1496cf27-b2dd-47d7-8077-1a23d14ae471 (old id 1148966)
date added to LUP
2008-05-09 12:59:31
date last changed
2016-09-19 08:44:45
@phdthesis{1496cf27-b2dd-47d7-8077-1a23d14ae471,
  abstract     = {This thesis discusses modeling and implementation of reconfigurable hardware<br/><br>
architectures for real-time applications. The target application in this work<br/><br>
is digital holographic imaging, where visible images are to be reconstructed<br/><br>
based on holographic recordings. The reconstruction process is computationally<br/><br>
demanding and requires hardware acceleration to achieve real-time performance.<br/><br>
Thus, this work presents two design approaches, with different levels<br/><br>
of reconfigurability, to accelerate the image reconstruction process and related<br/><br>
computationally demanding applications.<br/><br>
<br/><br>
The first approach is based on application-specific hardware accelerators, which<br/><br>
are usually required in systems with high constraints on processing performance,<br/><br>
physical size, or power consumption, and are tailored for a certain<br/><br>
application to achieve high performance. Hence, an acceleration platform<br/><br>
is proposed and designed to enable real-time image reconstruction in digital<br/><br>
holographic imaging, constituting a set of hardware accelerators that are connected<br/><br>
in a flexible and reconfigurable pipeline. Hardware accelerators are<br/><br>
optimized for high computational performance and low memory requirements.<br/><br>
The application-specific design has been integrated into an embedded system<br/><br>
consisting of a microprocessor, a high-performance memory controller, a digital<br/><br>
image sensor, and a video output device. The system has been prototyped<br/><br>
using an FPGA platform and synthesized for a 0.13 μm standard cell library,<br/><br>
achieving a reconstruction rate of 30 frames per second running at 400 MHz.<br/><br>
<br/><br>
The second approach is based on a dynamically reconfigurable architecture<br/><br>
to accelerate arbitrary applications, which presents a trade-off between versatileness<br/><br>
and hardware cost. The proposed reconfigurable architecture is constructed<br/><br>
from processing and memory cells, which communicate using a combination<br/><br>
of local interconnects and a global network. High-performance local<br/><br>
interconnects generate a high communication bandwidth between neighboring<br/><br>
cells, while the global network provides flexibility and access to external memory.<br/><br>
The processing and memory cells are run-time reconfigurable to enable<br/><br>
flexible application mapping. Proposed reconfigurable architectures are modeled<br/><br>
and evaluated using Scenic, which is a system-level exploration environment<br/><br>
developed in this work. A design with 16 cells is implemented and synthesized<br/><br>
for a 0.13 μm standard cell library, resulting in low area overhead when<br/><br>
compared with application-specific solutions. It is shown that the proposed<br/><br>
reconfigurable architecture achieves high computation performance compared<br/><br>
to traditional DSP processors.},
  author       = {Lenart, Thomas},
  issn         = {1654-790X},
  keyword      = {Stream Processing,Digital Holography,Reconfigurable Computing,Reconfigurable Architectures,Run-time Reconfiguration,Design Exploration,Hybrid floating-point,Data Scaling,FFT,ASIC},
  language     = {eng},
  pages        = {175},
  publisher    = {The Department of Electrical and Information Technology},
  school       = {Lund University},
  series       = {Series of licentiate and doctoral thesis},
  title        = {Design of Reconfigurable Hardware Architectures for Real-time Applications},
  volume       = {5},
  year         = {2008},
}